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preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 19879 rev: b amendment/ 0 issue date: april 1997 AM79C983A integrated multiport repeater 2 (imr2) distinctive characteristics n repeater functionality compliant with ieee 802.3 repeater unit speci?ations n hardware implementation of management information base (mib) with all of the counters, attributes, actions, and noti?ations speci?d by ieee 802.3 section 19 (layer management) n twelve pseudo aui (paui) ports to support multiple media types via direct connection to external transceivers n one ieee-compliant aui port n one reversible aui (raui) port that can be programmed as a second aui port or used to connect directly to a media access controller (mac) n direct interface with the amd am79c988a quiet (quad integrated ethernet transceiver) to support 10base-t repeater designs n port switching support to allow individual ports to be switched between multiple ethernet backplanes under software control n remote monitoring (rmon) register bank to provide direct support for etherstatsentry and etherstatshistory object groups of the rmon mib (ietf rfc1757) n packet report port to provide packet information for deriving objects in the host, hosttopn, and matrix groups of the rmon mib (ietf rfc1578) n two user-selectable expansion bus modes: imr/imr+ compatible mode and asynchronous mode n simple 8-bit microprocessor interface n full led support n 132-pin pqfp cmos device with a single 5-v supply general description the AM79C983A integrated multiport repeater 2 (imr2) chip is a vlsi integrated circuit that provides a system-level solution to designing intelligent (man- aged) multiport repeaters. when the imr2 device is combined with the quad integrated ethernet trans- ceiver (quiet) device, it provides a cost-effective solution to designing 10base-t managed repeaters. the imr2 device integrates the repeater functions speci?d by section 9 ( repeater unit ) and section19 ( layer management for 10 mb/s baseband repeaters ) of the ieee 802.3 standard. the AM79C983A imr2 device provides 1 standard attachment unit interface (aui) port, 12 pseudo attachment unit interface (paui) ports, and 1 reversible aui (raui) port for direct connection to a media access controller (mac). the pseudo aui ports can be connected to external transceivers to support multiple media types, including 10base2, 10base-t, and 10base-fl/foirl. the pseudo aui ports can be turned off individually (without ex- ternal circuitry) to allow the switching of transceiver ports between imr2 devices. this capability allows multiple imr2 devices to be connected to a single set of transceivers, thus allowing straightforward implementations of port switching applications. the imr2 device also provides a hardware imple- mented management information base (himib), which is a super set of the functions provided by the am79c987 himib device. all of the necessary counters, attributes, actions, and noti?ations speci- ed by section 19 of the ieee 802.3 standard are included in the imr2 device. to facilitate the design of managed repeaters, the imr2 device implements a simple 8-bit microprocessor interface. support for an rmon mib, as speci?d by the internet engineering task force (ietf) rfc 1757, is provided. direct support is from an rmon register bank. addi- tional support is provided by the packet report port, which supplies information that can be used in conjunc- tion with a microprocessor to derive various rmon mib attributes. with systems using multiple imr2 de-
2 AM79C983A preliminary vices , the inf or mation is passed to a designated imr2 de vice that tr ansf ers the inf or mation to a ma c . f or application e xamples on b uilding fully-managed repeaters using the imr2 and quiet de vices , ref er to amd s imr2 t echnical man ual (pid 19898a).
AM79C983A 3 preliminary block diagram do di ci rdo rdi rci pdo pdi pci pdo pdi pci dat req ack col jam eclk macen frame ld[7:0] bsel crs colx part link pol d[7:0] cs c/ d rd wr rdy int sdata[3:0] dir[1:0] mclk rst xena pdat pclk penai penao ptag pdrv aui port raui port paui port 0 paui port 11 attributes and control registers (himib) receiver mac engine imr2 repeater engine manchester encoder transceiver interface manchester decoder pll fifo preamble jam fifo control packet report port microprocessor interface led interface expansion bus xmode 19879 b -1
4 AM79C983A preliminary rela ted amd pr oducts p ar t no. description am79c981 integ r ated multipor t repeater+ (imr+) am79c982 b asic integ r ated multipor t repeater ( b imr) am79c987 hardw are implemented management inf or mation base (himib) am79c988a quad integ r ated ether net t r ansceiv er (quiet) am7990 local area netw or k controller f or ether net (lance) am7996 ieee 802.3/ether net/cheaper net t r ansceiv er am79c90 cmos local area netw or k controller f or ether net (c-lance) am79c98 t wisted p air ether net t r ansceiv er (tpex) am79c100 t wisted p air ether net t r ansceiv er plus (tpex+) am79c900 integ r ated local area comm unications controller (ila cc) am79c940 media access controller f or ether net (ma ce) am79c960 pcnet-isa single-chip ether net controller (f or isa b us) am79c961 pcnet-isa+ single-chip ether net controller f or isa (with microsoft?plug n pla y?suppor t) am79c961a pcnet-isa ii full duple x single-chip ether net controller f or isa am79c965 pcnet-32 single-chip 32-bit ether net controller am79c970 pcnet-pci single-chip ether net controller (f or pci b us) am79c970a pcnet-pci ii full duple x single-chip ether net controller (f or pci b us) am79c974 pcnet-scsi combination ether net and scsi controller f or pci systems
AM79C983A 5 preliminary connection diagram pqfp 132 1 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 am79c983 v dd pci[1 1] pdi[1 1] pci[10] pdi[10] av ss pci[9] pdi[9] av ss pci[8] pdi[8] pci[7] pdi[7] pci[6] pdi[6] av ss pci[5] pdi[5] v dd pci[4] pdi[4] pci[3] pdi[3] pci[2] pdi[2] pci[1] pdi[1] pci[0] pdi[0] v dd rdi rdi+ a v ss do do+ di di+ ci ci+ dv ss macen col ack xmode req da t jam v dd eclk frame dv ss pdrv pda t ptag pclk dv ss penao penai dv ss matchi m atcho ps v dd int rdy dv ss rdo? rdo+ rci rci+ dv ss dir[1] dir[0] sda t a[3] dv ss sda t a[2] sda t a[1] sda t a[0] v dd xena rst dv ss mclk dv ss bsel crs colx p ar t link v dd pol ld[7] ld[6] dv ss ld[5] ld[4] dv ss ld[3] ld[2] wr rd cs c/ d data[7] data[6] data[5] data[4] dv ss data[3] data[2] data[1] data[0] v dd pdo[11] pdo[10] pdo[9] pdo[8] dv ss pdo[7] pdo[6] v dd pdo[5] pdo[4] dv ss pdo[3] pdo[2] v dd pdo[1] pdo[0] ld[0] ld[1] nc a 19879 b -2
6 AM79C983A preliminary logic symbol logic dia gram do di ci dir [1:0] mclk sdata [3:0] rst rdo rdi rci pdo pdi pci pdat pclk penai penao ptag pdrv xena xmode ld[7:0] bsel dat req ack col jam eclk crs colx macen frame part link pol d[7:0] cs c/ d rd wr rdy int dv ss av ss v dd expansion bus led interface microprocessor interface transceiver interface aui raui paui (12) packet report port am79c983 a 19879b -3 repeater state machine paui port 11 paui port 0 packet report port transceiver interface microprocessor interface expansion bus led interface aui port raui port mac engine 19879b -4
AM79C983A 7 preliminary or dering inf ormation standar d pr oducts amd standard products are a v ailab le in se v er al pac kages and oper ating r anges . the order n umber (v alid combi- nation) is f or med b y a combination of the elements belo w . valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. device number/description AM79C983A integ r ated multipor t repeater 2 (imr2) tempera ture range c = commercial (0?c to +70?c) optional pr ocessing blank = standard processing p a cka ge type k = plastic quad flat p ac k (pqb 132) al terna te p a cka ging option \w = t r immed and f or med in a tr a y \w AM79C983A c k device v aria tion blank = secur ity not included. s = secur ity included. (see appendix.) valid combinations AM79C983A kc, kc\w
8 AM79C983A preliminary table of contents distinctive characteristics .................................................................................................... 1 general description ................................................................................................................... 1 block diagram ............................................................................................................................... 3 related amd products ............................................................................................................... 4 connection diagram .................................................................................................................... 5 logic symbol ............................................................................................................................... .... 6 logic diagram ............................................................................................................................... . 6 ordering information ................................................................................................................. 7 standard products .......................................................................................................................... 7 pin designations .......................................................................................................................... 12 pin description ............................................................................................................................ 13 pseudo aui pins ........................................................................................................................... 13 raui port pins .............................................................................................................................. 13 aui pins ............................................................................................................................... ......... 13 expansion bus pins ...................................................................................................................... 13 packet report port ........................................................................................................................ 14 microprocessor interface .............................................................................................................. 15 led interface ............................................................................................................................... . 15 miscellaneous pins ....................................................................................................................... 15 transceiver device interface ........................................................................................................ 15 functional description ............................................................................................................ 17 overview ............................................................................................................................... ........ 17 basic repeater functions ............................................................................................................. 17 repeater function .................................................................................................................. 17 signal regeneration ............................................................................................................... 17 jabber lockup protection ....................................................................................................... 17 collision handling ................................................................................................................... 17 fragment extension ............................................................................................................... 17 auto partitioning/reconnection .............................................................................................. 17 basic management functions ....................................................................................................... 18 repeater management ........................................................................................................... 18 rmon ............................................................................................................................... ..... 18 packet reports ....................................................................................................................... 18 detailed functions ........................................................................................................................ 22 reset ............................................................................................................................... ....... 22 hardware reset ............................................................................................................... 22 software reset ................................................................................................................ 22 expansion bus ....................................................................................................................... 22 synchronous mode operation ......................................................................................... 23 asynchronous mode operation ....................................................................................... 24 packet statistics ..................................................................................................................... 24 packet report port ........................................................................................................... 24 raui port ......................................................................................................................... 25 error packet statistics ............................................................................................................ 26 transceiver interface .................................................................................................................... 26 paui ports .............................................................................................................................. 26 quiet device control and status data interface ................................................................... 26 quiet device control and status data interface operation ........................................... 26 control and status for non-quiet transceivers ............................................................. 27 visual status monitoring (led) support ....................................................................................... 27 using aui/raui for 10base-t ports ..................................................................................... 28 intrusion protection ....................................................................................................................... 28 timer values .......................................................................................................................... 29
AM79C983A 9 preliminary microprocessor interface .............................................................................................................. 29 management functions .......................................................................................................... 29 status register ................................................................................................................ 30 register bank 0: repeater registers .............................................................................. 30 source address match register .............................................................................. 30 total octets .............................................................................................................. 31 transmit collisions ................................................................................................... 31 configuration register ............................................................................................. 31 repeater status ....................................................................................................... 31 quiet device transceiver id register .................................................................... 31 repeater device and revision register .................................................................. 32 device configuration ................................................................................................ 32 register bank 1: interrupts .............................................................................................. 32 port partition status change interrupt ..................................................................... 32 runts with good fcs interrupt ................................................................................ 32 link status change interrupt ................................................................................... 32 loopback error change interrupt ............................................................................. 33 polarity change interrupt ......................................................................................... 33 sqe test error change interrupt ............................................................................. 33 source address changed interrupt .......................................................................... 33 intruder interrupt ...................................................................................................... 33 source address match interrupt .............................................................................. 33 data rate mismatch interrupt .................................................................................. 34 transceiver interface status .................................................................................... 34 transceiver interface change interrupt ................................................................... 34 jabber interrupt ........................................................................................................ 34 register bank 2: interrupt control registers ................................................................... 34 partition status change interrupt enable ................................................................. 34 runts with good fcs interrupt enable .................................................................... 34 link status change interrupt enable ....................................................................... 35 loopback error change interrupt enable ................................................................ 35 polarity change interrupt enable ............................................................................. 35 sqe test error change interrupt enable ................................................................ 35 source address changed interrupt enable ............................................................. 35 intruder interrupt enable .......................................................................................... 35 multicast address pass enable ................................................................................ 36 data rate mismatch interrupt enable ...................................................................... 36 last source address compare enable .................................................................... 36 preferred address compare enable ........................................................................ 36 transceiver interface changed interrupt enable ..................................................... 36 jabber interrupt enable ............................................................................................ 36 register bank 3: port control registers .......................................................................... 37 alternative reconnection algorithm enable ............................................................. 37 link test enable ...................................................................................................... 37 link pulse transmit enable ..................................................................................... 37 automatic receiver polarity reversal enable .......................................................... 37 sqe mask enable .................................................................................................... 37 port enable/disable ................................................................................................. 37 port switching control .............................................................................................. 37 extended distance enable ....................................................................................... 38 automatic last source address intrusion control ................................................... 38 automatic preferred source address intrusion control ........................................... 38 last source address lock control ........................................................................... 38 register bank 4: port status registers ........................................................................... 39 partitioning status of ports ....................................................................................... 39 link test status of ports .......................................................................................... 39 loopback error status ............................................................................................. 39 receive polarity status ............................................................................................ 39
10 AM79C983A preliminary sqe test status ...................................................................................................... 39 register bank 5: rmon registers .................................................................................. 39 etherstatsoctets ...................................................................................................... 39 etherstatspkts .......................................................................................................... 39 etherstatsbroadcastpkts .......................................................................................... 40 etherstatsmulticastpkts ............................................................................................. 40 etherstatscrcalignerrors ........................................................................................ 40 etherstatsundersizepkts .......................................................................................... 40 etherstatsoversizepkts ............................................................................................ 40 etherstatsfragments ................................................................................................ 40 etherstatsjabbers .................................................................................................... 40 etherstatscollisions ................................................................................................. 40 etherstats64octets .................................................................................................. 40 etherstats65to127octets ......................................................................................... 40 etherstats128to255octets ....................................................................................... 40 etherstats256to511octets ....................................................................................... 40 etherstats512to1023octets ..................................................................................... 40 etherstats1024to1518octets ................................................................................... 40 activity ...................................................................................................................... 40 register bank 7: management support ........................................................................... 40 device id .................................................................................................................. 40 sample error status ................................................................................................. 40 report packet size .................................................................................................. 41 stats control ......................................................................................................... 41 register banks 16 through 30: port attribute registers .................................................. 41 readable frames ..................................................................................................... 42 readable octets ...................................................................................................... 42 frame check sequence (fcs) errors ..................................................................... 42 alignment errors ...................................................................................................... 42 frames too long ..................................................................................................... 42 short events ............................................................................................................. 43 runts ........................................................................................................................ 43 collisions .................................................................................................................. 43 late events .............................................................................................................. 43 very long events ..................................................................................................... 43 data rate mismatches ............................................................................................. 43 auto partitions .......................................................................................................... 44 source address changes ........................................................................................ 44 readable broadcast frames ................................................................................... 44 last source address ................................................................................................ 44 readable multicast frames ..................................................................................... 44 preferred source address ........................................................................................ 44 system applications .................................................................................................................. 45 imr2 to quiet connection ........................................................................................................... 45 other media ............................................................................................................................... ... 45 mac interface ............................................................................................................................... 45 raui port ............................................................................................................................... 45 pr port configuration ............................................................................................................ 45 port switching ............................................................................................................................... 48 absolute maximum ratings ..................................................................................................... 50 operating ranges ................................................................................................................. 50 dc characteristics over operating ranges unless otherwise specified ............................... 50 switching characteristics over operating ranges unless otherwise specified ............... 51 key to switching waveforms ................................................................................................ 54 switching waveforms .............................................................................................................. 54 master clock (mclk) timing ........................................................................................................ 54
AM79C983A 11 preliminary expansion bus asynchronous clock (eclk) timing ................................................................... 54 expansion bus input timing - synchronous mode ....................................................................... 55 expansion bus output timing - synchronous mode .................................................................... 55 expansion port collision timing - synchronous mode ................................................................. 56 packet report port timing ............................................................................................................ 56 expansion port input timing - asynchronous mode ..................................................................... 56 expansion port output timing - asynchronous mode .................................................................. 57 paui pdo transmit ...................................................................................................................... 57 paui pci receive ......................................................................................................................... 57 paui receive ............................................................................................................................... . 58 (r)aui timing ............................................................................................................................... . 58 (r)aui receive ............................................................................................................................. 58 microprocessor bus interface timing ........................................................................................... 59 physical dimensions .................................................................................................................. 60
12 AM79C983A preliminary pin designa tions listed b y pin number pin no . pin name pin no . pin name pin no . pin name pin no. pin name 1 do- 34 wr 67 ld[2] 100 a v ss 2 do+ 35 rd 68 ld[3] 101 rdi+ 3 di- 36 cs 69 d v ss 102 rdi- 4 di+ 37 c/ d 70 ld[4] 103 v dd 5 ci- 38 d[7] 71 ld[5] 104 pdi[0] 6 ci+ 39 d[6] 72 d v ss 105 pci[0] 7 d v ss 40 d[5] 73 ld[6] 106 pdi[1] 8 ma cen 41 d[4] 74 ld[7] 107 pci[1] 9 col 42 d v ss 75 pol 108 pdi[2] 10 a ck 43 d[3] 76 v dd 109 pci[2] 11 xmode 44 d[2] 77 link 110 pdi[3] 12 req 45 d[1] 78 p ar t 111 pci[3] 13 d a t 46 d[0] 79 colx 112 pdi[4] 14 j am 47 v dd 80 crs 113 pci[4] 15 v dd 48 pdo[11] 81 bsel 114 v dd 16 eclk 49 pdo[10] 82 d v ss 115 pdi[5] 17 frame 50 pdo[9] 83 mclk 116 pci[5] 18 d v ss 51 pdo[8] 84 d v ss 117 a v ss 19 pdr v 52 d v ss 85 rst 118 pdi[6] 20 pd a t 53 pdo[7] 86 xena 119 pci[6] 21 pt a g 54 pdo[6] 87 v dd 120 pdi[7] 22 pclk 55 v dd 88 sd a t a[0] 121 pci[7] 23 d v ss 56 pdo[5] 89 sd a t a[1] 122 pdi[8] 24 pena o 57 pdo[4] 90 sd a t a[2] 123 pci[8] 25 penai 58 d v ss 91 d v ss 124 a v ss 26 d v ss 59 pdo[3] 92 sd a t a[3] 125 pdi[9] 27 ma tchi 60 pdo[2] 93 dir[0] 126 pci[9] 28 ma tcho 61 v dd 94 dir[1] 127 a v ss 29 ps 62 pdo[1] 95 d v ss 128 pdi[10] 30 v dd 63 pdo[0] 96 rci+ 129 pci[10] 31 int 64 ld[0] 97 rci- 130 pdi[11] 32 rd y 65 ld[1] 98 rdo+ 131 pci[11] 33 d v ss 66 nc 99 rdo- 132 v dd
AM79C983A 13 preliminary pin description pseudo a ui pins pdo 0-11 pseudo a ui data output output/high impedance pdo is a single-ended output dr iv er . pdo can be placed into a high impedance state , allo wing m ultiple imr2 de vices to connect to a single quiet de vice (por t s witching). the output data is manchester encoded. pdi 0-11 pseudo a ui receive data input input the input data is manchester encoded. pci 0-11 pseudo a ui collision input input p a ui por t collision data receiv er . a 10-mhz square w a v e indicates a collision has been detected on that por t. ra ui p or t pins rdo+, rdo- re ver sib le a ui data output output rdo is a diff erential, manchester output dr iv er . rdi+, rdi- re ver sib le a ui data input input rdi is a diff erential, manchester receiv er . rci+, rci- re ver sib le a ui collision input input/output rci is a diff erential i/o . as an input, rci receiv es a col- lision indication. as an output, rci gener ates a 10-mhz square w a v e when a collision is sensed. ps output this pin is reser v ed f or f actor y use . a ui pins do+, do- a ui data output output a ui por t diff erential dr iv er . manchester encoded data. di+, di- a ui data input input a ui por t diff erential receiv er . manchester encoded data. ci+, ci- a ui collision input input a ui por t collision diff erential receiv er . expansion bus pins d a t data input/output/high impedance the imr2 de vice dr iv es the d a t line with nrz data when both req and a ck pins are asser ted. d a t is an input if only the a ck signal is asser ted. if req and a ck are not asser ted, d a t enters a high impedance state . dur ing collision when j am is high, d a t is used to sig- nal a m ultipor t (d a t=0) or single por t (d a t=1) condition. j am jam input/output/high impedance this pin is an output if the de vice is the only activ e imr2 de vice . an imr2 de vice is de ned as activ e when it has one or more por ts receiving or colliding, is in the state where it is still tr ansmitting data from the inter nal fifo , or is e xtending a pac k et to the minim um 96-bit times . if activ e , the imr2 de vice dr iv es the j am pin high to indicate that it is in a collision state when both req and a ck pins are asser ted. j am is an input if only the a ck signal is asser ted. if req and a ck are not as- ser ted, j am enters a high impedance state . req request output, active lo w this pin is dr iv en lo w when the imr2 de vice senses activity . an imr2 de vice is de ned as a ctive when it has one or more por ts receiving or colliding, is in the state where it is still tr ansmitting data from the inter nal fifo , or is e xtending a pac k et to the minim um 96-bit times . the asser tion of this signal signi es that the imr2 de vice requires the d a t and j am lines to tr ansf er repeated data and collision status inf or mation to other imr2 de vices . a ck ac kno wledg e input, active lo w when this signal is asser ted b y an e xter nal arbiter , it signals to the requesting imr2 de vice that it ma y dr iv e the d a t and j am pins . it signals to other imr2 de vices the presence of v alid collision status on the j am line and v alid data on the d a t line .
14 AM79C983A preliminary col collision input, active lo w when this pin is asser ted b y an e xter nal arbiter , it sig- ni es that more than one imr2 de vice is activ e and that each imr2 de vice should gener ate the collision j am sequence independently . eclk bus cloc k input/output data tr ansitions on the e xpansion b us on d a t are syn- chroniz ed to this cloc k. eclk is a 10-mhz output cloc k when d a t is tr ansmitting and a 10-mhz input cloc k when d a t is receiving. eclk is only used when the e x- pansion b us is oper ated in the asynchronous mode . eclk should be ter minated to g round with a 1 k w resis- tor . eclk should be ignored in the synchronous mode . ma cen ma c enab le input, active lo w when this pin is asser ted, data on the e xpansion b us is included in mib statistics . this is typically used when a ma c is dr iving the e xpansion b us . ma tcho this pin should be tied to +5 v through a 1 k w 10% resistor . ma tchi this pin should be tied to +5 v through a 1 k w 10% resistor . frame p ac ket framing signal input/output, active lo w frame de nes the beginning and end of a pac k et. frame indicates v alid data on the d a t pin when the e x- pansion b us is in the asynchronous mode . frame is an output on the imr2 de vice when it is tr ansmitting o v er the e xpansion b us . it is an input on all other imr2 de vices . xmode expansion bus mode input xmode deter mines the mode of the e xpansion b us . xmode should not be changed after rst . although changing xmode after rst will change the e xpansion b us mode , the oper ation is unpredictab le . theref ore , it is recommended that xmode be tied either high or lo w , depending on the desired e xpansion b us mode . xena p or t enab le input xena sets the def ault mode of the por ts . it is used when rst tr ansitions from lo w to high. note: xena only controls the def ault state . once reset is completed, the enab ling and disab ling of por ts is under softw are control. it is recommended that xena be tied either high or lo w , depending on the desired def ault state . p ac ket repor t p or t pd a t p ac ket repor t output, high impedance pd a t outputs the beginning por tion of a pac k et f ol- lo w ed b y pac k et status inf or mation. the siz e of the be- ginning por tion is user prog r ammab le . if a second pac k et arr iv es bef ore pd a t nishes tr ansmitting status inf or mation, the second pac k et and corresponding sta- tus inf or mation are not tr ansmitted o v er pd a t . the pac k et is abor ted on collision. penai p ac ket repor t enab le input input, active lo w penai senses when another de vice is tr ansmitting o v er pd a t . pena o p ac ket repor t enab le output output, active lo w , open drain pena o is tr ue when the imr2 de vice is tr ansmitting data o v er pd a t . if a second pac k et arr iv es bef ore pd a t is nished tr ansmitting status inf or mation, pena o re- mains activ e f or the second pac k et. pdr v p ac ket drive output, active lo w pdr v is tr ue when the imr2 de vice is tr ansmitting data o v er pd a t . if a second pac k et arr iv es bef ore pd a t is nished tr ansmitting status , pdr v goes f alse after the status is tr ansmitted. pclk p ac ket repor t cloc k output, high impedance pclk is a 10-mhz cloc k. pd a t tr ansitions are synchro- niz ed to pclk. xmode mode 1 asynchronous 0 synchronous (imr/imr+) xena default 1 all por ts are enab led. 0 all por ts are disab led. the output dr iv ers are in a high impedance state .
AM79C983A 15 preliminary pt a g p ac ket t a g output, high impedance , active lo w pt a g indicates when the status fr ame is being tr ans- mitted o v er pd a t . it is asser ted when the status fr ame is tr ansmitted. micr opr ocessor interface d[7:0] micr opr ocessor data input/output these pins are inputs when either cs or wr are lo w . the y are outputs when cs and rd are lo w . other- wise , these pins are high impedance . cs chip select input, active lo w this pin enab les the imr2 de vice to read from or wr ite to the microprocessor data b us . c/ d contr ol/data input this pin is used to select either a control register or a data register in the imr2 de vice and is nor mally con- nected to the least signi cant bit of the address b us . rd read str obe input, active lo w initiates read oper ation. wr write str obe input, active lo w initiates wr ite oper ation. rd y read y output, active high, open drain rd y is dr iv en lo w at the star t of e v er y read or write cycle . rd y is released when the imr2 de vice is ready to complete the tr ansaction. int interrupt output, active lo w , open drain the interr upt pin is dr iv en lo w when an y of the un- mask ed (enab led) interr upts occur . led interface ld[7:0] led driver s output ld is the status output and is tr ansmitted as 2 b ytes . the b yte n umber (high or lo w) is deter mined b y bsel. bsel byte select output when bsel is lo w , ld[7:0] is tr ansmitting the status of the rst eight p a ui por ts (por ts p 7 through p 0 ). when bsel is high, ld[7:0] is tr ansmitting the status of the rest of the p a ui por ts (por ts p 11 through p 8 ), the a ui por t, the ra ui por t, and the e xpansion b us . crs carrier sense str obe output when crs is high, ld [7:0] has carr ier sense status . colx collision status output when colx is high, ld [7:0] has collision status . p ar t p ar titioning status output when p ar t is high, ld [7:0] has par titioning status . link link status output when link is high, ld [7:0] has link status . pol p olarity status output when pol is high, ld [7:0] has polar ity status . miscellaneous pins rst reset input when rst is lo w , the imr2 de vice resets to its def ault state . mclk master cloc k input mclk is a 20-mhz cloc k input. t ransceiver de vice interface sd a t a [3:0] serial data input/output sd a t a carr ies command and status data betw een the imr2 de vice and the quiet de vice (or other connected tr ansceiv er). pin t ransceiver p or ts sd a t a [0] p a ui [3:0] sd a t a [1] p a ui [7:4] sd a t a [2] p a ui [11:8] sd a t a [3] arbitr ar y por ts
16 AM79C983A preliminary dir direction output dir sets the direction of data on sd a t a[3:0] the set- tings are as f ollo ws: v dd p o wer pin these pins supply +5 v po w er . a v ss analog gr ound gr ound pin these pins pro vide the g round ref erence f or the analog por tions of the imr2 circuitr y . these pins should be de- coupled and k ept separ ate from the digital g round plane . d v ss digital gr ound gr ound pin these pins pro vide the g round ref erence f or the digital por tions of the imr2 circuitr y . these pins should be de- coupled and k ept separ ate from the analog po w er plane . dir[1:0] function 00 t r ansceiv er (quiet de vice) dr iv es sd a t a with status and de vice id . 01 sd a t a is a high impedance output. 10 sd a t a is a high impedance output. 11 imr2 de vice dr iv es sd a t a with commands .
AM79C983A 17 preliminary functional description over vie w the AM79C983A integ r ated multipor t repeater 2 de- vice pro vides a system-le v el solution to designing ieee 802.3 managed repeaters . it includes 12 pseudo a ui (p a ui) por ts f or single-ended connections to e xter nal tr ansceiv ers . the imr2 de vice interf aces directly with amd's am79c988a quad integ r ated ether net t r ans- ceiv er (quiet) de vice f or 10base-t implementations . the p a ui por ts can be tur ned off individually to enab le por t s witching applications . in addition, the imr2 de- vice has a standard a ui por t and a re v ersib le a ui (ra ui) por t f or a direct connection to a ma c . the imr2 de vice pro vides a hardw are implemented management inf or mation base (himib) which contains all of the necessar y counters , attr ib utes , actions , and noti cations speci ed b y section 19 of the ieee 802.3 standard. suppor t f or an rmon mib , as speci ed b y the inter net engineer ing t ask f orce (ietf) rfc 1757, is also pro vided. direct suppor t is from an rmon reg- ister bank. additional suppor t is pro vided b y the p ac k et repor t p or t, which supplies pac k et inf or mation that can be used in conjunction with a microprocessor to der iv e v ar ious rmon mib attr ib utes . basic repeater functions the imr2 repeater functions are summar iz ed belo w . an o v er vie w of imr2 management functions is presented under basic management functions . repeater function if an y single netw or k por t of a repeater system senses the star t of a v alid pac k et on its receiv e lines , the imr2 de vice will retr ansmit the receiv ed data to all other en- ab led netw or k por ts unless a collision is detected. the repeated data will also be presented on the d a t line of the e xpansion b us to f acilitate designs utilizing m ultiple imr2 de vices . the imr2 de vice fully complies with section 9.5.1 of the ieee 802.3 speci cations . signal reg eneration when retr ansmitting a pac k et, the imr2 de vice en- sures that the outgoing pac k et complies with the ieee 802.3 speci cation in ter ms of preamb le str ucture . data pac k ets repeated b y the imr2 de vice will contain a minim um of 56 preamb le bits bef ore the star t of f r ame delimiter . the imr2 de vice , b y vir tue of its inter nal phase loc k loop and manchester encoder/decoder , will ensure correct regener ation of the repeated signal at its p a ui and a ui outputs . if the outputs of the imr2 de vice are connected to quiet de vice tr ansceiv ers , the 10base-t outputs of the quiet de vices will meet the ieee 802.3 signal symmetr y requirements . if other types of tr ans- ceiv ers are used, the signal char acter istics will depend, in par t, on the tr ansceiv er . jabber loc kup pr otection the imr2 chip implements a b uilt-in jab ber protection scheme to ensure that the netw or k is not disab led due to tr ansmission of e xcessiv ely long data pac k ets . this protection scheme will automatically interr upt the tr ansmitter circuits of the imr2 de vice f or 96-bit times , if the imr2 de vice has been tr ansmitting contin uously f or more than 65,536 bit times . this is ref erred to as ma u j ab ber loc kup protection (mjlp). the mjlp status f or the imr2 chip can be read from the repeater status register . collision handling the imr2 chip will detect and respond to collision con- ditions as speci ed in the ieee 802.3 speci cation. a m ultiple imr2 de vice repeater implementation also complies with the speci cation because of the inter- imr2 chip status comm unication pro vided b y the e x- pansion por t. speci cally , a repeater based on one or more imr2 de vices will handle correctly the tr ansmit collision and one-por t-left collision conditions as spec- i ed in section 9 of the ieee 802.3 speci cation. fra gment extension if the total pac k et length receiv ed b y the imr2 de vice is less than 96 bits , including preamb le , the imr2 chip will e xtend the repeated pac k et length to 96 bits b y ap- pending a j am sequence to the or iginal fr agment. note that in a f e w cases , it is possib le f or the imr2 de vice to gener ate a sequence 97 bits in length when the e xpan- sion b us is oper ated in the asynchronous mode . a uto p ar titioning/reconnection an y of the imr2 por ts can be par titioned under e xces- siv e dur ation or frequency of collision conditions . once a por t is par titioned, the imr2 de vice will contin ue to tr ansmit data pac k ets to a par titioned por t, b ut will not respond (as a repeater) to activity on the par titioned por t s receiv er . the imr2 chip will monitor the por t and reconnect it once cer tain cr iter ia indicating por t ? ell- ness are met. the cr iter ia f or reconnection are speci- ed b y the ieee 802.3 standard. in addition to the standard reconnection algor ithm, the imr2 de vice im- plements an alter nativ e reconnection algor ithm which pro vides a more rob ust par titioning function. each por t is par titioned and/ or reconnected separ ately and inde- pendently of other netw or k por ts . either one of the f ollo wing conditions occurr ing on an y enab led imr2 de vice netw or k por t will cause the por t to par tition: a. an sqe signal activ e f or more than 2048 bit times . b . a collision condition occurs dur ing each of 32 con- secutiv e attempts to tr ansmit to that por t. once a netw or k por t is par titioned, the imr2 de vice will reconnect that por t if the f ollo wing is met:
18 AM79C983A preliminary a. standard reconnection algor ithm? data pac k et longer than 512-bit times (nominal) is tr ansmitted or re- ceiv ed b y the par titioned por t without a collision. b . alter nate reconnection algor ithm? data pac k et longer than 512-bit times (nominal) is tr ansmitted b y the par titioned por t without a collision. basic mana g ement functions repeater mana g ement the imr2 management functions are a super-set of the those pro vided b y the amd s imr+/himib de vice chipset. the imr2 de vice contains the complete set of repeater and por t functions as de ned in ansi/ieee 802.3, repeater management standard , (section 19). all mandator y and optional capabilities are suppor ted. these include the basic control, p erf or mance monitor- ing, and address t r ac king pac kages . additionally , node address mapping, ma u management speci c functions , and intr usion protection functions are in- cluded. suppor t is also pro vided f or the rmon mib rfc 1757. all inf or mation is stored in registers which can be ac- cessed through the microprocessor interf ace (node processor p or t). the register location is de ned b y a register bank and an address within that register bank. address and data of the registers are m ultiple x ed using the c/ d pin. the register address is selected b y wr iting to the node processor p or t with c/ d high. the regis- ter data is selected b y wr iting or reading to the node processor p or t with c/ d lo w . man y of the registers are larger than 1 b yte . f or these registers , consecutiv e accesses to register data (equal to the n umber of b ytes in the register) are required. the order is lsbyte to msbyte . f or a wr ite oper ation, if the address changes bef ore all the b ytes are wr itten, the register is not changed to the ne w v alue . the status register is accessed b y reading the node processor p or t with the c/ d pin high. this reduces the n umber of oper ations necessar y to access the status register . all bit elds are ordered such that the left most bit is the most signi cant bit. un used register banks , por ts and register n umbers are reser v ed and should not be ac- cessed as this ma y cause de vice malfunction. when specifying the register bank or por t n umber , the f ollo w- ing f or mat is used : p4:0 represent the register bank or p or t number , or- ganiz ed as f ollo ws: p = p 4 p 3 p 2 p 1 p 0 p p or t/register bank 0 repeater registers 1 interr upt registers 2 interr upt control registers 3 p or t control registers 4 p or t status registers 5 rmon registers 7 p ac k et repor t registers 16- 30 p or t attr ib utes the register to be accessed f or reading or wr iting is speci ed b y wr iting the f ollo wing control b yte to the c register : r = r 4 r 3 r 2 r 1 r 0 figure 1 sho ws the management register map , and t ab le 1 sho ws register banks and register assignments within the register banks . rmon remote monitor ing (rmon) functions are designed to giv e the management system the capability to remotely monitor the hub f or diagnostic pur poses . the r ules f or rmon are descr ibed in the rmon mib (as of this wr iting ietf rfc1578). the imr2 de vice pro vides direct suppor t f or both the statistics and histor y object g roups . indirect suppor t is pro vided f or the alar m, host, hostt opn, e v ent, and ma- tr ix g roups . direct suppor t is pro vided via the rmon register set and rele v ant attr ib ute registers . indirect suppor t is pro vided through the p ac k et repor t p or t. p ac ket repor ts the imr2 de vice gener ates status inf or mation on e v er y pac k et that it repeats . the data is tr ansmitted o v er the p ac k et repor t p or t. the data f or mat consists of the beginning of the pac k et f ollo w ed b y a pac k et tag and statistical data on the pac k et . 0 0 0 p4 p3 p2 p1 p0 c p or t wr ite msb lsb 1 1 1 r4 r3 r2 r1 r0 c p or t wr ite msb lsb preamb le d a sa t/l p ac k et data v ar . length t ag & fcs p or t no ., ne w status
AM79C983A 19 preliminary figure 1. mana g ement register map 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bank select 8 register select status register 5 5 0 0 0 p4 p3 p2 p1 p0 0 1 2 3 4 5 7 16 * * 27, 28, 29, 30 rr ir icr pcr ps rmn msr p0 * * p11, a, ar, ep c/ d = 0 1 1 1 r4 r3 r2 r1 r0 to node processor port a - aui port ar - raui port ep - expansion port icr - interrupt control registers ir - interrupt registers msr - management support registers pcr - port control registers ps - port status registers pxx - paui port rmn - rmon registers rr - repeater registers to node processor port command (c) port 8 8 c/ d = 1 data (d) port 19879b -5
20 AM79C983A preliminary t ab le 1. mana g ement register s reg. no. register bank 0 repeater register s register bank 1 interrupt register s register bank 2 interrupt contr ol register s register bank 3 p or t contr ol register s 0 p or t p ar tition status change interr upt p ar tition change interr upt enab le alter nativ e p ar tition algor ithm enab le 1 runts with good fcs interr upt runts with good fcs interr upt enab le 2 link status change interr upt link status change interr upt enab le link t est enab le 3 loopbac k error change interr upt loopbac k error change interr upt enab le link pulse t r ansmit enab le 4 p olar ity change interr upt p olar ity change interr upt enab le a utomatic receiv er p olar ity re v ersal enab le 5 sqe t est error change interr upt sqe t est error change interr upt enab le sqe mask enab le 6 source address changed interr upt source address changed interr upt enab le p or t enab le/disab le 7 intr uder interr upt intr uder interr upt enab le p or t mobility control 8 source address match interr upt extended distance enab le 9 multicast address p ass enab le last source address a utomatic intr usion control 10 source address match register data rate mismatch interr upt data rate mismatch interr upt enab le pref . source address a utomatic intr usion control 11 last source address loc k enab le 12 t otal octets last source address compare enab le 13 t r ansmit collisions 14 15 t r ansceiv er interf ace status pref erred address compare enab le 16 con gur ation register t r ansceiv er interf ace changed interr upt t r ansceiv er interf ace changed interr upt enab le 17 j ab ber interr upt j ab ber interr upt enab le 18 19 20 21 22 23 24 25 26 repeater status 27 quiet de vice id register 28 repeater de vice and re vision register 29 de vice con gur ation 30 31
AM79C983A 21 preliminary t ab le 1. mana g ement register s (contin ued) reg. no. register bank 4 p or t status register s register bank 5 rmon register s register bank 7 mana g ement suppor t register s register bank 16-30 p or t attrib ute register s 0 p ar titioning status of p or ts etherstatsoctets de vice id readab le f r ames 1 etherstatspkts readab le octets 2 link t est status of p or ts etherstatsbroadcastpkts sample error status f r ame chec k sequence errors 3 loopbac k error status etherstatsmulticastpkts repor t p ac k et siz e alignment errors 4 receiv e p olar ity status etherstatscrcalignerrors statistics control f r ames t oo long 5 sqe t est status etherstatsundersiz epkts shor t ev ents 6 etherstatsov ersiz epkts runts 7 etherstatsf r agments collisions 8 etherstatsj ab bers late ev ents 9 etherstatscollisions v er y long ev ents 10 etherstats64octets data rate mismatches 11 etherstats65to127octets a uto p ar tition 12 etherstats128to255- octets source address changes 13 etherstats256to511- octets readab le broadcast f r ames 14 etherstats512to1023- octets last source address 15 etherstats1024to1518- octets readab le multicast f r ames 16 activity pref erred source address 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
22 AM79C983A preliminary detailed functions this section describes the detailed functional behavior of the imr2 device. where necessary, the behavior is detned in terms of state machines. note that this is a conceptual detnition and the actual implementation may be different. reset hardware reset the imr2 device enters the reset state when the rst pin is driven low. the reset pin should be held low for a minimum of 150 m s after power-up or 4 m s other- wise. this allows the imr2 device to reset the internal logic. during reset, the registers are set to their default values. the output signals are placed in their inactive state. that is, all analog outputs are placed in their idle state, all bidirectional signals are not driven, all active- high signals are driven low, and all active-low sig- nals are driven high. the only exception is pol, which defaults to high on reset. in a multiple imr2 device re- peater, the reset signal should be synchronized to mclk when the expansion bus is operated in the syn- chronous mode. reset does not affect the rmon registers (register bank 5) or the port attribute registers (register banks 16-30). these registers will power up at a random value. they can be preset while the imr2 is in software reset or while the port is disabled via the microprocessor interface. the mode of the expansion bus and the default state of the ports are set by xmode and xena during rst . xmode sets the expansion bus mode and xena sets the port state. note that xena only controls the default state. once reset is completed, the enabling and dis- abling of the ports is under software control. the settings are as follow: software reset the imr2 device supports software reset with two bits on the device contguration register: repeater reset (r - bit 7 on the register) and management reset (m - bit 6 on the register). bit r resets the registers, repeater, and mac engine. setting bit r is the functional equiva- lent of hardware reset, with the exception that the micro- processor interface is not reset and the ability to access 4 and 6 byte attribute registers is maintained. bit m af- fects only the management and intrusion protection functions of the imr2 device. bit r causes the imr2 device to go into the default state. as with hardware reset, all analog outputs are placed in their idle state, all bidirectional signals are not driven, all active-high signals are driven low, and all active-low signals are driven high. the only excep- tion is pol, which defaults to high on reset. registers are also set to their default state. setting bit r also allows write access to the mib regis- ters and some other read-only registers. these regis- ters are the total octets register, the transmit collision register, the entire rmon register bank, and the port attribute register banks. note that the last source ad- dress register and the preferred source address reg- ister can also be written into when bit r is not set. setting bit r will not affect any bit of the device contg- uration register. thus, the imr2 device does not auto- matically exit software reset. software reset must be exited by setting bit r to zero. the function of bit m is a subset of the function of bit r. it affects the intrusion protection and mib registers. set- ting bit m causes the intrusion protection registers to go into the default state. as with bit r, the mib registers can be written into. 2 lists the default state of the registers. if the m column has an m, the corresponding register is set to its default state when bit m is set. expansion bus the expansion bus has two modes of operation: the synchronous (imr/imr+ compatible) mode and the asynchronous mode. the modes are differentiated by the expansion bus clock. in the synchronous mode, the imr2 devices (and any imr/imr+ devices) are all clocked by a single 20-mhz clock. the imr2 device uses mclk as the clock source. in the asynchronous mode, imr2 devices can be clocked (mclk) by different sources. the single imr2 device transmitting over the expansion bus provides the clock source for data. the clock pin in this mode is eclk. eclk clocks the data. all other expansion bus signals are asynchronous. the mode of expansion bus operation is selected during reset by xmode. the expansion bus can be contgured for connection to a mac. the pin ma cen selects the mac mode. when ma cen is true (low), the statistics on the data re- ceived by dat are recorded in the management regis- ters. the expansion bus is considered another port in the same sense as the pauis, the aui, and the raui. xmode 1 the expansion bus is in the asynchronous (imr2) mode. 0 the expansion bus is in the synchronous (imr/imr+) mode. xena 1 all ports are enabled. 0 all paui ports are disabled. the output drivers are placed in a high impedance state.
AM79C983A 23 preliminary sync hr onous mode operation while oper ating in the synchronous mode , the e xpan- sion b us pins are data (d a t), j am, request ( req ), ac kno wledge ( a ck ), and collision ( col ). d a t and j am are bidirectional signals . req is an output. a ck and col are inputs . the imr2 de vice e xpansion scheme allo ws the use of m ultiple imr2 de vices in a single-board repeater or in a modular m ultipor t repeater with a bac kplane architec- ture . data sent on the d a t line is in nrz f or mat and is synchroniz ed to mclk. another bidirectional pin, j am, is used to comm unicate inter nal imr2 de vice status from the single activ e imr2 de vice to other imr2 de- vices in the system. this signal indicates whether the activ e imr2 de vice is in a collision state . arbitr ation f or control of the b ussed signals , d a t and j am, is pro vided b y e xter nal circuitr y . one output pin ( req ) and tw o input pins ( a ck and col ) are used as arbitr ation signals . the imr2 de vice asser ts req to t ab le 2. register reset default states register default m cont gur ation enab le interr upts source address match interr upt mask ed mask ed m, r repeater status mjlp no error r de vice cont gur ation repeater reset management reset ra ui direction loopbac k t est mode t r ansceiv er loopbac k nor mal nor mal nor mal nor mal nor mal p ar tition change interr upt none r runts with good fcs interr upt none m, r link change interr upt none r loopbac k change interr upt none r p olar ity changed interr upt none r sqe t est no change interr upt none r source address changed interr upt none m, r intr uder interr upt none m, r source address match interr upt none m, r data rate mismatch interr upt no mismatch r t r ansceiv er interf ace status no t r ans . r t r ansceiv er interf ace change interr upt none r j ab ber interr upt no j ab ber r p ar tition change interr upt enab le mask ed r runts with good fcs interr upt enab le mask ed m,r link changed interr upt enab le mask ed r loopbac k changed interr upt enab le mask ed r p olar ity changed interr upts enab le mask ed r sqe t est changed interr upt enab le mask ed r register default m source address changed interr upt enab le mask ed m,r intr uder interr upt enab le mask ed m, r multicast address p ass enab le disab led m, r data rate mismatch interr upt enab le mask ed r source address compare enab le disab led m, r pref erred address compare enab le disab led m, r t r ansceiv er interf ace changed interr upt enab le mask ed r j ab ber interr upt enab le mask ed r alter nativ e p ar tition disab led r link t est enab le enab led r link pulse enab le enab led r re v erse p olar ity enab le disab led r sqe mask enab le disab led r p or t enab le enab led r p or t mobility control xena r extended distance control enab le disab led r source address a utomatic intr u- sion enab le disab led r pref erred address a utomatic intr u- sion enab le disab led r last source address loc k enab le disab led m, r p ar tition status connect r link status link f ail r loopbac k status no error r p olar ity status p ositiv e r sqe t est status no error r sample counter que f our m, r p ac k et repor t p ac k et siz e 07ff? m, r statistics control stat t ag fcs t ag disab le disab le m, r m, r
24 AM79C983A preliminary indicate that it is activ e and is ready to dr iv e the d a t and j am signals . the e xter nal arbiter asser ts a ck if one and only one imr2 de vice has req asser ted. this allo ws the corresponding imr2 de vice to dr iv e the d a t line with data to be repeated b y all other imr2 de vices . if there is more than one imr2 de vice asser ting req , the e xter nal arbiter should asser t col , indicating m ul- tiple imr2 de vices are activ e . the activ e imr2 de vice dr iv es the j am line high in order to signal other imr2 de vices that it has detected a collision across one or more of its por ts and is gener- ating a j am sequence . the d a t line is used dur ing sin- gle imr2 de vice collision (j am asser ted) to signal single-por t collision (d a t high) or m ultipor t collision (d a t lo w). other imr2 de vices synchroniz e their in- ter nal collision j am sequence gener ators using j am and d a t pins as inputs . if more than one imr2 de vice is activ e (m ultiple req s asser ted), the e xter nal arbiter should asser t the col line to signal this condition. in this case , all imr2 de- vices in the repeater are f orced into the m ultipor t colli- sion state and will gener ate j am sequence independently while this condition lasts . as por ts on separ ate imr2 de vices bac k off , the last imr2 de vice with an activ e por t regains control of the d a t and j am signals and all other imr2 de vices will contin ue gener- ating j am sequence while the j am signal is asser ted. in a typical single-board application, three imr2 de- vices can be connected together without the use of e x- ter nal tr ansceiv ers . the total n umber of imr2 de vices that can be used in a more comple x architecture will depend on the dr iv e capability , system timing limita- tions , and system design. the e xter nal arbiter is required to gener ate tw o signals ( a ck and col ). the logic function f or these signals in a three imr2 de vice repeater unit is as f ollo ws: a ck = req1 & !req2 & !req3 + !req1 & req2 & !req3 + !req1 & !req2 & req3 col = !(a ck + !req1 & !req2 & !req3) async hr onous mode operation the oper ation of the e xpansion b us in the asynchro- nous mode is similar to the oper ation in the synchro- nous mode . the pr imar y diff erence is that the cloc k signal in the asynchronous mode is eclk, which is sourced b y the imr2 de vice tr ansmitting d a t . the sig- nals j am, req , a ck , and col are all asynchronous . d a t is synchroniz ed to eclk, which is a 10-mhz cloc k signal. when the imr2 de vice asser ts req and re- ceiv es an a ck , eclk is an output. when the imr2 de- vice does not asser t req and receiv es an a ck , eclk is an input. in the asynchronous mode , it is probab le that eclk and the master cloc ks of the receiving imr2 de vices will be sk e w ed in frequency . t o help the imr2 de vices accom- modate the frequency diff erences , the e xpansion b us tr ansmits a fr aming signal ( frame ). see figure 2 . because j am is an asynchronous signal, there is no det ned relationship betw een j am and eclk. figure 2. async hr onous mode data t ransf er p ac ket statistics p ac ket repor t p or t f or each pac k et, the imr2 de vice can compile a set of data about that pac k et. this data, which will no w be re- f erred to as the repor t pac k et, allo ws the system to de- r iv e objects in the host, hostt opn, and matr ix g roups of the rmon mib (rfc 1757). the repor t p ac k et is deliv ered b y the p ac k et repor t p or t (pr). the pr por t tr ansmits a por tion of the pac k et along with data about that pac k et to a ma c . the f or mat of the repor t pac k et is sho wn in 3 . sending only a por tion of the pac k et is ref erred to as pac k et compression. the deg ree to which the or iginal pac k et is compressed is set b y the repor t p ac k et siz e register . the siz e is in b ytes . if the register is set to 14 or less , the siz e of the pac k et passed is 14 b ytes . if the register is set to 1536 or g reater , the entire pac k et is passed. if the pac k et siz e is equal to or less than the v alue set in the repor t p ac k et siz e register , the entire pac k et is passed. if the destination address of the pac k et is the same as the address of the ma c connected to the pr p or t, then it is desir ab le to ha v e the entire pac k et tr ansmitted to the ma c . theref ore , pac k et compression is automati- cally disab led when the destination address of the pac k et is a v alid address f or the e xpansion b us . ho w- e v er , the repor t tag is appended to the end of the pac k et. note that the entire pac k et is also sent if the destination address is a broadcast address . eclk frame dat jam ack 19879b -6
AM79C983A 25 preliminary figure 3. detailed repor t p ac ket the presence of a v alid destination address is deter- mined b y compar ing the destination address of the pac k et with the last source address register and the pref erred source address register associated with the e xpansion b us . compar ison is enab led b y setting the ep bit of the last source address compare enab le register and/or the pref erred source address compare enab le register . setting the ep bit of the multicast address p ass enab le register inhibits com- pression when the address is a m ulticast address . the pr por t has six signals: pclk, pd a t , pena o , penai , pdr v , and pt a g . pclk is a 10-mhz cloc k sig- nal. pd a t tr ansmits the pac k et data and is cloc k ed b y the r ising edge of pclk. pena o is an activ e-lo w sig- nal and indicates when the pr por t is activ e . penai senses when a pr por t of another imr2 de vice is ac- tiv e and is an activ e-lo w signal. pdr v is used to en- ab le an e xter nal b uff er f or pclk and pd a t . pt a g indicates when the tag is being tr ansmitted. the signal f or mat is sho wn in 4 . pd a t t rst tr ansmits the compressed or uncompressed pac k et. then it tr ansmits the t rst status t eld. this t eld has the f or mat of the t rst statistics t eld sho wn in 4 . at the end of the t rst statistics t eld, pclk is stopped until the end of the pac k et. then the second statistics t eld is tr ansmitted o v er pd a t along with a ne w fcs . multiple imr2 de vices can be connected to a single ma c . if an imr2 de vice becomes activ e while another de vice is tr ansmitting statistics , the ne w pac k et will not be tr ansmitted o v er the pr por t. ra ui p or t the ra ui p or t is a cont gur ab le a ui por t. it has the same signals that are associated with an a ui por t: do , di, and ci. f or the ra ui p or t, these are named rdo , rdi, and rci, respectiv ely . the ra ui por t can be con- t gured in either nor mal or re v erse mode . when cont g- ured in nor mal mode (def ault mode), the functionality is that of an a ui por t on a ma c . when cont gured in re- v erse mode , the ra ui por t pro vides the functionality of an a ui por t on a ma u , with rci acting as an output. this re v erse cont gur ation allo ws the ra ui p or t to be connected directly to a ma c . ho w e v er , the sense of rdo and rdi does not change with the cont gur ation. theref ore , in the re v erse cont gur ation rdo should be connected to di of the ma c and rdi should be con- nected to do on the ma c . t ab le 3. ra ui p or t br o ad - broadcast address match mul t - multicast address match res - reser v ed. set to zero . bre - bit rate error align - f r aming error crc - crc error preamb le and sfd f ront of or iginal p ac k et (min 14 octets long) br o ad mul t res res p or t number lsb f r ame siz e (in octets) r oll res bre align crc msb f r ame siz e (in octets) ne w fcs (4 octets) stat 1 field stat 2 field (4 bits) r oll- f r ame siz e has e xceeded 1535 b ytes note : the bit designation is lsb to the left and msb to the r ight. the t elds are tr ansmitted lsb t rst. de vice id 19879b -7 de vice cont guration register bit 5 ra ui p or t mode 0 nor mal mode 1 re v erse mode (rci is an output)
26 AM79C983A preliminary figure 4. p ac ket p or t signals err or p ac ket statistics sample error status is an 8-b yte 4-deep fifo that con- tains statistical data on each pac k et ha ving errors . the data is read in the f ollo wing order : the fifo is emptied b y reading. if the fifo is full, noth- ing more is recorded in sample error status . if the con- trol por t is accessed, the reading star ts at the beginning of the ne xt location. if the data register is accessed after the location has been completely read, the beginning of the ne xt location is automatically accessed. t ransceiver interface p a ui p or ts p ac k ets are tr ansf erred betw een an imr2 de vice and tr ansceiv ers via tw elv e pseudo a ui (p a ui) por ts . the p a ui por ts ha v e the functionality of a ui por ts , e xcept that the y are single-ended signals r ather than diff erential. quiet de vice contr ol and status data interface control and status data are passed betw een the imr2 de vice and quiet de vices via a ser ial data interf ace . status data is on the sd a t a[3:0] pins , and ser ial inter- f ace control is on the dir[1:0] pins . sd a t a is i/o . f or interf acing with non-quiet de vices , both dir[1] and dir[0] are required. dir[1:0] is used to select g roups of f our por ts . f or interf acing with quiet de vices , only dir[1] is required. dir[1] controls the direction of data tr a v el. each sd a t a pin corresponds to a quiet de vice connected to a set of f our specit c imr2 de vice por ts . t ypically , sd a t a[3] is not used f or a 12-por t repeater . ho w e v er , a quiet de vice can be attached to the a ui por t and the ra ui por t (in nor mal mode) to mak e a 14- por t repeater . the remaining tw o por ts on the quiet de vice can be connected to tw o por ts on another imr2 de vice . sd a t a[3] pro vides the ma u management f or all f our por ts on this quiet de vice . quiet de vice contr ol and status data interface operation the interf ace has tw o modes of oper ation: quiet de- vice mode and non-quiet de vice mode . the quiet de vice mode is automatically selected when a quiet de vice is attached and used, and the non-quiet mode is selected when another type of tr ansceiv er is used. note that it is possib le f or diff erent sets of por ts to use diff erent types of tr ansceiv ers . pre sfd da sa stat1 field t/l field stat2 field fcs pdat pclk pdrv penao ptag data length in bytes 19879b -8 p or t number 1 b yte status 1 b yte: fcs error (lsb) non-integ r al bytes long shor t runt data rate error v er y long ev ent (msb) source address 6 b ytes pin p or t sd a t a[0] p a ui [3:0] sd a t a[1] p a ui [7:4] sd a t a[2] p a ui [11:8]
AM79C983A 27 preliminary in the quiet de vice mode , dir[1] has the f ollo wing v alues: dir[1] 0 quiet de vice dr iv es sd a t a with sta- tus and de vice id . 1 imr2 de vice dr iv es quiet de vice with commands . dir[1] contin ually cycles . the state of dir changes once e v er y 50-bit times (1-bit time = 100 ns). when dir[1] s witches from 1 to 0, the quiet de vice re- sponds in the f ollo wing f or mat: 01010a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 d 0 d 1 d 2 d 3 s 0 s 1 s 2 s 3 each char acter corresponds to a bit. each bit is held f or 2- bit times (200 ns). the imr2 de vice uses the 01010 pre- amb le to deter mine if the tr ansceiv er is a quiet de vice . if an y other sequence is receiv ed, the sd a t a[n] pins be- ha v e as if a non-quiet de vice tr ansceiv er is connected. on the sd a t a[n] pins that retur n the correct preamb le , the imr2 de vice tr ansmits the f ollo wing sequence when dir[1] s witches from 0 to 1. 0e 0 e 1 e 2 e 3 f 0 f 1 f 2 f 3 g 0 g 1 g 2 g 3 h 0 h 1 h 2 h 3 s 0 s 1 s 2 s 3 s 4 s 5 s 6 contr ol and status f or non-quiet t ransceiver s on the sd a t a[n] pins that do not retur n the correct pre- amb le , the imr2 de vice e xpects to see data correspond- ing to the polar ity status of the por t. the corresponding signals f or each por t on the tr ansceiv er should be con- nected to a 4-to-1 m ultiple x er with dir utiliz ed as the control lines . the m ultiple x er should beha v e as f ollo ws: dir[1:0] rotates through the 10 ? 00 ? 01 ? 11 cycle regardless of the mode of sd a t a[n]. the mode of each sd a t a[n] pin can change with each cycle as tr ansceiv- ers are remo v ed or inser ted. visual status monitoring (led) suppor t the imr2 de vice has a status por t which can be con- nected to leds to f acilitate visual monitor ing of diff er- ent repeater por ts . fiv e por t status attr ib utes can be monitored: carr ier sense (crs), collision (colx), p ar tition (p ar t), link status (link), and p olar ity (pol). the status of the por ts is indicated on an 8-bit b us , ld[7:0], which is time m ultiple x ed to sho w all t v e attr ib utes f or up to 16 por ts . bsel is the por t select pin. when the select pin (bsel) is lo w , ld[7:0] has the status of por ts p7 through p0. when bsel is high, ld[3:0] has the status of p11 through p8, ld[4] has the status of the a ui por t, and ld[5] has the status of the ra ui por t. ld[7:6]is used to displa y the por t status of a f our th quiet de vice that optionally ma y be shared with another imr2 de vice . crs , colx, p ar t , link, and pol are the attr ib ute se- lect pins . when an attr ib ute select pin is high, ld[7:0] indicates the corresponding status attr ib ute . the status monitor ing por t contin ually cycles as per 5 . each strobe is activ e f or 64-bit times (6.4 m s). this allo ws a 10-per- cent duty cycle . the f ollo wing tab le giv es the v alue of ld[7:0] corresponding to the attr ib ute select signal. 01010 preamb le a 0 a 1 a 2 a 3 de vice id (0000 f or quiet) b 0 b 1 b 2 b 3 0 link f ail 1 link p ass c 0 c 1 c 2 c 3 0 receiv ed polar ity is re v ersed. 1 receiv ed polar ity is correct. d 0 d 1 d 2 d 3 0 no j ab ber 1 j ab ber s n spares - will be logic high. e 0 e 1 e 2 e 3 extended distance 0 disab led 1 enab led f 0 f 1 f 2 f 3 link t est 0 disab led 1 enab led g 0 g 1 g 2 g 3 link pulse t r ansmit 0 disab led 1 enab led h 0 h 1 h 2 h 3 re v erse receiv ed p olar ity 0 disab led 1 enab led s n spares - will be logic high. dir[1:0] action 00 select t r ansceiv er 0. 01 select t r ansceiv er 1. 10 select t r ansceiv er 2. 11 select t r ansceiv er 3. signal high lo w crs activity no activity colx collision no collision p ar t connected p ar titioned link good none pol correct re v ersed
28 AM79C983A preliminary figure 5. visual monitor signals crs and colx are the only v alid attr ib utes f or the ex- pansion bus . theref ore , when bsel is high, ld[6] has the expansion bus attr ib ute f or crs and colx. using a ui/ra ui f or 10b ase-t p or ts the imr2 de vice obtains link and p olar ity status from the ser ial data interf ace (sd a t a [3:0]). when a single imr2 de vice uses f our quiet de vices , tw o of the por ts on the f our th quiet de vice connect to the a ui and ra ui por ts of the imr2. the tw o remaining por ts on the f our th quiet de vice connect to a second imr2 de vice . only the imr2 de vice dr iving the ser ial interf ace to this quiet de vice has link and p olar ity status . theref ore , when bsel is high and either link or p ar t are high, ld[7:6] contains link status or p olar ity status , respectiv ely , of por ts 2 and 3 of the f our th quiet de- vice . if the a ui and ra ui por ts are connected to a ma u (other than a quiet de vice), link actually repor ts loopbac k error , where 1 indicates no loopbac k error and 0 indicates a loopbac k error . the state of pol will re? ect the receiv ed polar ity v alue on sd a t a. the rec- ommended implementation is sho wn in 6 . the attr ib ute select pins are connected to open-collector or open- dr ain in v er ters . the b uff ers connected to ld[7:0] ha v e high-impedance outputs . the y m ust source enough current to tur n on the leds (typically 20 ma). cmos de vices that ha v e a r ail-to-r ail output are recom- mended. also , m ultiple open-collector in v er ters can be used in conjunction with m ultiple dr iv es to o v ercome maxim um current source/dr ain issues . crs and colx signals are stretched to enhance vi- sual recognition, i.e ., the y will remain activ e f or some time e v en if the corresponding condition has e xpired. once carr ier sense is activ e , crs will remain activ e f or a minim um of 4 ms . once a collision is detected, colx will remain activ e f or at least 4 ms . figure 6. visual monitoring application - simplit ed sc hematic intrusion pr otection the imr2 de vice pro vides protection against intr usion, which is det ned here as the unauthor iz ed tr ansmitting of pac k ets onto the netw or k. each por t has tw o address registers associated with it: last source address register and pref erred source address register . unless it is loc k ed, the last source address register contains the source address of the pre vious pac k et receiv ed b y that por t. the pref erred source address register contains the source address that the system considers v alid f or that por t. both reg- isters ma y be wr itten. if the v alid address is kno wn b y the system, it ma y be wr itten into both registers . if it is not kno wn b y the sys- tem, the last source address register is monitored b y the system. after a pac k et is receiv ed b y the por t, the source address ma y be wr itten into the pref erred source address register b y the system. the last source address register ma y be loc k ed. if the last source address register is loc k ed, a mis- match betw een the pac k et's source address and the last source address register will not result in a change in the last source address register . the only w a y the register can be changed is b y accessing it through the node processor interf ace . the control reg- ister f or this is the last source address loc k register . the imr2 de vice pro vides tw o applicab le interr upts: source address changed interr upt and intr uder inter- r upt. both interr upts can be mask ed on a por t-b y-por t basis . source address changed interr upt compares the incoming pac k et's source address against tw o registers: last source address register and the pre- f erred source address register . the interr upt is set when the source address of the incoming pac k et does not match both registers . intr uder interr upt compares ld[7:0] bsel crs colx part link pol 19879b -9 ld [7:0] en en bsel crs colx part link pol 19879b -10
AM79C983A 29 preliminary the incoming pac k et's source address with the pre- f erred source address register . the interr upt is set when there is a mismatch. if the a utomatic intr usion control register bit is set, the por t is disab led if there is no match betw een the source address and either v alid source address f or that por t. v alid addresses are deter mined from the correspond- ing pref erred source address a utomatic intr usion control register and last source address a utomatic intr usion control register . the selection of these reg- isters as v alid addresses is made b y the last source address compare enab le register and the pref erred source address compare enab le register . the por t is disab led after the fcs t eld and only if the pac k et is a v alid pac k et. once the por t is disab led, it can only be enab led b y the management softw are . timer v alues descr iptions and v alues f or the v ar ious timers are as f ollo ws: micr opr ocessor interface the imr2 de vice implements a simple interf ace de- signed to be used b y a v ar iety of a v ailab le microproces- sors . the b us interf ace is asynchronous and can be easily adapted f or diff erent hardw are interf aces . the interf ace protocol is as f ollo ws: 1. asser t cs (lo w) and c/ d (high to access control and lo w to access data). 2. asser t rd (lo w) to star t a read cycle or wr (lo w) to star t a wr ite cycle . 3. the imr2 de vice f orces rd y lo w in response to the leading edge of either of rd or wr . note: cs is inter nally gated with rd and wr , such that cs ma y be per manently g rounded if it is not re- quired. a read or wr ite cycle is star ted when cs and ei- ther data strobe are asser ted (lo w). write cyc le : 1. data is to be placed on the data (d[7:0]) pins pr ior to tr ailing edge of wr . 2. the imr2 de vice releases rd y (pulled high e xter- nally), indicating that it is ready to accept the data. 3. wr strobe is de-asser ted (high) in response to rd y . the imr2 de vice latches data inter nally on the r ising edge of wr . 4. the processor can stop dr iving data pins after the r ising edge of the wr . man y of the registers are tw o or more b ytes long. in these cases , the registers are read or wr itten into b y ac- cessing the microprocessor por t with c/ d lo w the same n umber of times as the b yte siz e of the register . read cyc le : 1. the imr2 de vice dr iv es data pins . 2. the imr2 de vice releases rd y (pulled high), indi- cating v alid data. 3. de-asser t rd (high) in response to rd y high. 4. the imr2 de vice stops dr iving data pins after the tr ailing edge of rd . the interr upt pin ( int ) is an open dr ain output. it is off (high impedance) upon reset, when all interr upts are disab led (mask ed), or when all inter nal sources of the interr upts are cleared. it is on (lo w) when an y of the enab led interr upts occur . reading all the inter nal regis- ters that caused the interr upt clears the inter nal source of the interr upt, and sets int off . mana g ement functions all management functions are accessib le through the microprocessor interf ace . the functions are divided into register banks which are subdivided into attr ib ute regis- ters . a register bank is selected b y wr iting a b yte with the f or mat 000p 4 p 3 p 2 p 1 p 0 into the c por t, where p 4 through p 0 corresponds to the register bank. the de- sired attr ib ute register within the selected register bank is selected b y wr iting 111r 4 r 3 r 2 r 1 r 0 into the c por t, where r 4 through r 0 corresponds to the attr ib ute regis- ter . data can then be read from or wr itten to the d por t. f or registers whose contents are cleared upon reading, reading the t rst b yte will clear the entire register . when wr iting to registers , all b ytes m ust be wr itten consecu- tiv ely . if all register b ytes are not wr itten, the or iginal contents of the register are left unchanged. most of the registers contain status or control inf or ma- tion on the individual por ts . these registers are each tw o b ytes long. each bit corresponds to an individual por t. activ e statistics will be maintained on the data receiv ed b y d a t only if the ep bit of the p or t enab le register is set and ma cen is tr ue. t w1 w ait timer f or the end of tr ansmit reco v er y time 10 bit times t w2 w ait timer f or the end of carr ier reco v er y time 3 bit times t w3 w ait timer f or length of contin uous output 65,536 bit times t w4 w ait timer f or time to disab le output f or j ab ber loc kup protection 96 bit times t w5 w ait timer f or length of pac k et without collision 452 to 523 bit times t w6 w ait timer f or e xcessiv e length of collision 2048 bit times cc- limit number of consecutiv e collisions which m ust occur bef ore a segment (por t) is par titioned 32 collisions
30 AM79C983A preliminary unless otherwise indicated, the discussion of registers that are concer ned with status or control on the imr2 de vice will ha v e the f ollo wing f or mat. imr2 de vice register s where : p n ref ers to a p a ui por t. a ui ref ers to the a ui por t ra ui ref ers to the ra ui por t ep ref ers to the expansion bus unless otherwise indicated, the discussion of regis- ters that are concer ned with status or control on quiet de vices connected to the imr2 de vice will ha v e the f ollo wing f or mat. quiet de vice register s where: tpn ref ers to a tp por t on a quiet de vice . spn ref ers to a quiet de vice por t connected to the a ui por t or p a ui por t on this de vice or to an y por t on another imr2 de vice . note: the por t on the quiet de vice ma y be connected to a por t on another imr2 de vice . status register the status register can be accessed at an y time b y reading the command register . the 8-bit quantity read has the f ollo wing f or mat: i interr upt. this bit re? ects the state of the int output pin. if this bit is set to 1, then this imr2 de vice is dr iving the int pin. note that int is an open dr ain output and that m ultiple de vices ma y share the same interr upt signal. e t r ansceiv er interf ace changed. this bit is set if the interf ace to at least one sd a t a input has changed from a quiet de vice to a non-quiet de vice or from a non-quiet de vice to a quiet de vice . s source address match. this bit is set if the inter- r upt is caused b y a source address match of the incoming data pac k et. this bit remains set until the source address match status register is read. b bit rate error and p ar tition. this bit is set if the interr upt is caused b y either a bit r ate error or a change in the par tition status of a por t. m source address change . this bit is set if the inter- r upt is caused b y a change in the source address or a mismatch betw een the incoming source ad- dress and a pref erred address . p p olar ity and sqe. this bit is set if the interr upt is caused b y a change in the sqe test results or a polar ity change . l link and loopbac k . this bit is set if the interr upt is caused b y a link or loopbac k change . x reser v ed. the v alues of reser v ed bits are indeter minate . register bank 0: repeater register s these registers are accessed b y wr iting the bit patter n 0000 0000 to the c register . the contents of all at- tr ib ute counters are indeter minate upon po w er up . source address match register address: 1110 1010 this is a read/wr ite register . the six b ytes are read or wr itten in lo w b yte to high b yte order . the sequence is (re)star ted once the c register is prog r ammed f or ac- cess to this register . this register ma y be used to tr ac k nodes within a lan b y repor ting the por t that receiv ed a pac k et with a specit c source address . the source ad- dress t eld of incoming pac k ets is alw a ys compared with the 48-bit quantity stored in this register . the initial v alue of this register is indeter minate . the imr2 indicates a match b y setting the correspond- ing bit in the source address match interr upt register of the receiving por t. if the source address match in- terr upt enab le bit is enab led, then the int output pin is dr iv en lo w . the set bit(s) in the source address match interr upt registers are cleared when these reg- isters are read. note: once the sequence is star ted, all six b ytes ha v e to be wr itten or the contents do not change . p7 p6 p5 p4 p3 p2 p1 p0 0 ep/0 ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp 10 tp9 tp8 byte 0 byte 1 d port read/write i e s x b m p l c p or t read bit 7 bit 0 bit 47 bit 40 d p or t read/wr ite msb lsb byte 0 byte 4 byte 5 byte 2 byte 3 byte 1
AM79C983A 31 preliminary t otal octets address: 1110 1100 this is a 4-b yte attr ib ute register whose contents are in- cremented while the repeater is repeating pac k et data. this counter is a tr uncated divide b y 8 of the total n um- ber of bits tr ansmitted b y the repeated (i.e ., the n umber of whole b ytes tr ansmitted b y the repeater). the counter counts the b ytes on all non-collision pac k ets with a v alid star t of f r ame delimiter (sfd). the pre- amb le is included in the count. the f our b ytes in this at- tr ib ute are sequentially accessed b y reading the d register , lsb t rst. note that once the c register is pro- g r ammed f or access to this attr ib ute , reading the d reg- ister por t causes the v alue of this register to be copied into the holding register . the data is then read off the holding register , without aff ecting this attr ib ute . this se- quence is repeated when the last b yte is read and the d register is accessed. t r ansmit collisions address: 1110 1101 this is a 4-b yte attr ib ute whose contents are incre- mented each time the repeater has entered the tr ans- mit collision state from an y state other than one por t left . the b ytes are read in lo w to high order b y reading the data (d) register consecutiv ely . the se- quence will be restar ted once the last b yte is read or the c register is reprog r ammed with this register n um- ber . this causes the current v alue of the counter to be copied into a holding register , which is then read b y ac- cessing the d register . cont gur ation register address: 1111 0000 this is a read/wr ite register . the v alue read is the same as that wr itten. un used bits are read as z eros and only z eros should be wr itten into these bits . do not wr ite non-z ero v alues into un used bits . all bits are cleared upon reset. i enab le interr upts . when this bit is set to 0 all inter- r upts from this imr2 de vice are mask ed (b ut not cleared) and the int output pin is f orced into inac- tiv e state (not dr iv en). s source address match interr upt enab le . when this bit is set, imr2 de vice will gener ate an interr upt if the source address of the receiv ed pac k et match- es that which is prog r ammed into the source ad- dress match register . repeater status address: 1111 1010 this is a read only register . bit 0 is the only bit of inter- est. when bit 0 is set, the imr2 de vice has entered ma u j ab ber loc kup protection (mjlp). the repeater status register is cleared b y reading. e status 0 no error 1 error quiet de vice t r ansceiv er id register address: 1111 1011 this is a read-only register . it contains the tr ansceiv er id of the quiet de vice connected to the imr2 de vice . the 16-bit quantity has the f ollo wing f or mat: t r ansceiv er 0 p a ui [3:0] t r ansceiv er 1 p a ui [7:4] t r ansceiv er 2 p a ui [11:8] t r ansceiv er 3 a ui and ra ui por ts or misc. this 16-bit register is divided into f our sections . each section is labeled m x3 to m x0 where x ref ers to tr ans- ceiv ers 0 through 3. these register bits are only v alid if the appropr iate t r ansceiv er interf ace status register bit indicates that a quiet de vice is connected. bit 7 bit 0 bit 31 bit 24 d p or t read/wr ite m sb lsb byte 0 byte 2 byte 1 byte 3 bit 7 bit 0 bit 31 bit 24 d p or t read/wr ite msb lsb byte 0 byte 1 byte 2 byte 3 i 0 s 0 0 0 0 0 d p or t read / wr ite msb lsb 0 0 0 0 0 0 0 e d p or t read msb lsb t r ansceiv er 1 t r ansceiv er 0 m 13 m 12 m 11 m 10 m 03 m 02 m 01 m 00 t r ansceiv er 3 t r ansceiv er 2 m 33 m 32 m 31 m 30 m 23 m 22 m 21 m 20 d port read byte 1 byte 0 msb lsb
32 AM79C983A preliminary m x3-x0 t ransceiver 0 quiet de vice id 1 to 15 reser v ed repeater de vice and re vision register address: 1111 1100 this is a read only register . the 8-bit quantity read has the f ollo wing f or mat: d de vice t ype . these bits contain the imr2 de vice code . d3-0 0010 imr2 v re vision number . these bits contain the re vision n umber . softw are ma y interrogate these bits to de- ter mine additional f eatures that ma y be a v ailab le with future v ersions of the de vice . v3-0 0000 re vision 0 de vice cont gur ation address: 1111 1101 this is a read/wr ite register . when this register is wr it- ten, z eros m ust be wr itten into unassigned t elds . the 8-bit quantity has the f ollo wing f or mat: r repeater reset. setting bit r resets the registers , repeater , and ma c engine . it is the functional equiv alent of hardw are reset, with the e xception that the microprocessor interf ace is not reset and the ability to access rmon and por t attr ib ute reg- isters is maintained. m management reset. setting this bit causes the ma c engine to be reset. when the m bit is set, the imr2 de vice still functions as a repeater , ho w e v er mib tr ac king is disab led. setting this bit also allo ws the rmon registers and the attr ib ute registers to be preset b y softw are . a this bit cont gures the ra ui por t. the cont gur a- tion options are: 0 nor mal mode . the ra ui por t is cont gured as a standard a ui por t. 1 re v erse mode . rci is an output, i.e ., rci gener ates a 10-mhz signal dur ing a collision. register bank 1: interrupts when a bit on an interr upt register is set, the interr upt bit on the status register is set and the int pin is dr iv en. these registers are accessed b y wr iting the bit patter n 0000 0001 to the c register . these registers are read only and are cleared to 0 upon reading. when all the interr upt registers are clear (all bits z ero), the in- terr upt bit of the status register and int are cleared. note that f or each interr upt register there is a corre- sponding interr upt enab le register . the bits on the inter- r upt register cannot set unless the corresponding bits on the corresponding interr upt enab le register are set. p or t p ar tition status change interr upt address: 1110 0000 an y por t changing state betw een par titioned and re- connected causes the appropr iate register bit to be set to 1. the f or mat is as f ollo ws: pn/a ui/ra ui 0 p ar tition status of corresponding por t unchanged 1 p ar tition status of corresponding por t changed runts with good fcs interr upt address: 1110 0001 an y por t receiving a pac k et that is less than 64 octets (not including preamb le and sfd), b ut is otherwise w ell f or med and error free , causes the appropr iate bit to be set. the f or mat is as f ollo ws: pn/a ui/ra ui/ep 0 no r unts with v alid fcs 1 runt with v alid fcs link status change interr upt address: 1110 0010 a change in the link t est state of a twisted pair por t associated with a repeater por t (from f ail to pass or pass to f ail) causes the appropr iate bit to be set in this register . this register is only v alid when a quiet de vice is connected to the corresponding por t(s). d3 d2 d1 d0 v3 v2 v1 v0 d p or t read msb lsb r m a 0 0 0 0 0 d port read/write msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read byte 0 byte 1 lsb msb p7 p6 p5 p4 p3 p2 p1 p0 0 ep ra ui a ui p11 p10 p9 p8 d port read byte 0 byte 1 msb lsb tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp 10 tp9 tp8 byte 0 byte 1 d port read lsb msb
AM79C983A 33 preliminary tpn/spn 0 link t est state unchanged 1 link t est state changed loopbac k error change interr upt address: 1110 0011 if a por t is connected to a ma u which does not loop- bac k data from do to di dur ing tr ansmission that por t has a loopbac k error . f or the error to be detected, the netw or k needs to be activ e and a pac k et tr ansmitted from the por t. the corresponding bit is set to 1 when the loopbac k error condition changes . pn/a ui/ra ui 0 no loopbac k error change 1 loopbac k error change p olar ity change interr upt address: 1110 0100 the corresponding bit is set to 1 if the polar ity of the connected por t is s witched. tpn/spn 0 p olar ity unchanged 1 p olar ity changed sqe t est error change interr upt address: 1110 0101 if a por t is connected to a ma u with sqe t est enab led that por t has an sqe t est error . f or the error to be de- tected, the netw or k needs to be activ e and a pac k et m ust be tr ansmitted from the por t. the corresponding bit on the register is set when the por t changes from an error state to a non-error state or from a non-error state to an error state . pn/a ui/ra ui 0 no sqe t est error change 1 sqe t est error change source address changed interr upt address: 1110 0110 the corresponding bit in the register is set when the source address of the incoming data pac k et matches neither the last source address register nor the pre- f erred source address register associated with the por t. the incoming pac k et m ust be an error-free pac k et. pn/a ui/ra ui/ep 0 no change 1 source address changed on the incoming por t intr uder interr upt address: 1110 0111 a bit on the intr uder interr upt register is set when the source address of an error-free incoming pac k et does not match the corresponding pref erred source address reg- ister . the incoming pac k et m ust be an error-free pac k et. note: the pref erred address attr ib ute is prog r amma- b le and can be used to store the e xpected node id f or a por t. if the appropr iate interr upt is also enab led, then a source address changed can be used to aler t the netw or k manager of an unauthor iz ed access . this is par ticular ly useful f or segments that are supposed to be connected to a single station. pn/a ui/ra ui/ep 0 intr uder status of por t unchanged 1 intr uder status of por t changed source address match interr upt address: 1110 1000 when the source address of an incoming pac k et from an y por t matches the source address match register , the appropr iate bit is set. the receiv ed pac k et m ust be an error-free pac k et. p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read byte 0 byte 1 lsb msb tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp 10 tp9 tp8 byte 0 byte 1 d port read lsb msb p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read byte 0 byte 1 lsb msb p7 p6 p5 p4 p3 p2 p1 p0 0 ep ra ui a ui p11 p10 p9 p8 d port read byte 0 byte 1 lsb msb p7 p6 p5 p4 p3 p2 p1 p0 0 ep ra ui a ui p11 p10 p9 p8 d port read byte 0 byte 1 lsb msb p7 p6 p5 p4 p3 p2 p1 p0 0 ep ra ui a ui p11 p10 p9 p8 d port read byte 0 byte 1 lsb msb
34 AM79C983A preliminary pn/a ui/ra ui/ep 0 no match 1 source address matches the source address match register note: this function is useful f or mapping stations to por ts in a netw or k. data rate mismatch interr upt address: 1110 1010 a bit is set when the data receiv ed b y the corresponding por t has caused an o v er? o w or under? o w of the fifo . this bit is not set unless the receiv ed pac k et, after sfd , is at least 512 bits long and collision did not occur pn/a ui/ra ui/ep 0 no error 1 data r ate error t r ansceiv er interf ace status address: 1110 1111 if a quiet tr ansceiv er is not hardw are connected, the corresponding bit on the register is set . quiet 0 (q0) p a ui [3:0] quiet 1 (q1) p a ui [7:4] quiet 2 (q2) p a ui [11:8] quiet 3 (q3) a ui and ra ui por ts qn 0 quiet de vice is connected 1 non-quiet tr ansceiv er is connected t r ansceiv er interf ace change interr upt address: 1111 0000 if the de vice changes from a quiet de vice to another type of tr ansceiv er or from a non-quiet de vice to a quiet de vice , the corresponding bit on the register is set. quiet 0 (q0) p a ui [3:0] quiet 1 (q1) p a ui [7:4] quiet 2 (q2) p a ui [11:8] quiet 3 (q3) a ui and ra ui por ts qn 0 no change of tr ansceiv er type 1 change of tr ansceiv er type j ab ber interr upt address: 1111 0001 a bit on this register is set if the tr ansceiv er connected to the corresponding por t detects jab ber . tpn/spn 0 p or t does not jab ber 1 p or t in jab ber register bank 2: interrupt contr ol register s these registers are accessed b y wr iting the bit patter n 0000 0010 to the c register . all registers can be read from as w ell as wr itten to . a set (1) control bit enab les an interr upt or function of the corresponding por t. all control registers are cleared upon reset. also , all inter- r upts are disab led and all status bits are cleared upon hardw are reset. p ar tition status change interr upt enab le address: 1110 0000 this register is used to enab le or mask interr upts caused b y a change in the p or t p ar titioning status . note that if this is the only cause f or the interr upt, dis- ab ling an activ e interr upt source causes the int output to be placed into an inactiv e state . softw are should be designed to wr ite z eros into un used bits . pn/a ui/ra ui 0 p ar tition status change interr upt mask ed (disab led) 1 p ar tition status change interr upt enab led runts with good fcs interr upt enab le address: 1110 0001 this register is used to enab le or mask interr upts caused b y a por t receiving a pac k et that is less than 64 octets (not including preamb le and sfd), b ut is other- wise w ell f or med and error free . p7 p6 p5 p4 p3 p2 p1 p0 0 ep ra ui a ui p11 p10 p9 p8 d port read byte 0 byte 1 lsb msb x x x q3 q2 q1 q0 d p or t read x msb lsb x x x q3 q2 q1 q0 d p or t read x msb lsb tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp 10 tp9 tp8 byte 0 byte 1 d port read msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 ep ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 msb lsb
AM79C983A 35 preliminary pn/a ui/ra ui/ep 0 runts with v alid fcs interr upt mask ed (disab led) 1 runts with v alid fcs interr upt enab led link status change interr upt enab le address: 1110 0010 setting an y of the bits in this register causes the int pin to be dr iv en when there is a change in the link t est state of the corresponding por t. the corresponding sta- tus bit in the link t est state change register is set to 1. tpn/spn 0 link status change interr upt mask ed (disab led) 1 link status change interr upt enab led loopbac k error change interr upt enab le address: 1110 0011 setting a bit in this register causes an interr upt to be gener ated when the imr2 de vice senses a change in the loop bac k error condition on the corresponding por t. pn/a ui/ra ui 0 loopbac k error change interr upt mask ed (disab led) 1 loopbac k error change interr upt enab led p olar ity change interr upt enab le address: 1110 0100 setting a bit in this register causes an interr upt to be gener- ated when the polar ity of the connected por t is changed. tpn/spn 0 p olar ity change interr upt mask ed (disab led ) 1 p olar ity change interr upt enab led sqe t est error change interr upt enab le address: 1110 0101 setting a bit in this register causes an interr upt to be gener ated when the imr2 de vice senses a change in the sqe t est error condition at a por t. this occurs when an attached ma u has sqe t est enab led. a ne w interr upt is gener ated when a condition change is sensed b y the imr2 de vice . pn/a ui/ra ui 0 sqe t est error change interr upt mask ed (disab led) 1 sqe t est error change interr upt enab led source address changed interr upt enab le address: 1110 0110 this register enab les interr upts caused b y a mismatch betw een the source address of an incoming pac k et and either the last source address register or the pref erred source address register . if last source address loc k is not set and the pac k et is a v alid pac k et, a mismatch betw een the source address and the last source address register also causes the ne w source address to be wr itten into the last source address register . pn/a ui/ra ui/ep 0 source address changed interr upt mask ed (disab led) 1 source address changed interr upt enab led intr uder interr upt enab le address: 1110 0111 this register enab les interr upts to be gener ated when the source address of an incoming pac k et does not match the pref erred source address register on the corresponding por t. the corresponding interr upt can be inter preted as an attempt b y an intr uder to gain access to the netw or k. the management system can then tak e appropr iate ac- tion, such as disab ling the corresponding por t. pn/a ui/ra ui 0 intr uder interr upt mask ed (disab led) 1 intr uder interr upt enab led tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp10 tp9 tp8 byte 0 byte 1 d port read/write msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 lsb msb tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp 10 tp9 tp8 byte 0 byte 1 d port read msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 ep ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 ep ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 msb lsb
36 AM79C983A preliminary multicast address p ass enab le address: 1110 1001 setting ep disab les pac k et compression on pac k ets with m ulticast addresses . ep 0 p ac k et compression on pac k- ets with m ulticast addresses is enab led 1 p ac k et compression on pac k- ets with m ulticast addresses is disab led note: zeros should be wr itten to all register bits e x- cept the ep bit. data rate mismatch interr upt enab le address: 1110 1010 the imr2 de vice can gener ate an interr upt if receiv ed data is outside the data r ate toler ances . setting a bit enab les the data rate mismatch interr upt control of the corresponding por t. pn/a ui/ra ui/ep 0 data rate mismatch interr upt mask ed (disab led) 1 data rate mismatch interr upt enab led last source address compare enab le address: 1110 1100 setting the ep bit in this register enab les a compar ison of the destination address of an incoming pac k et to the last source address register f or the e xpansion por t. p ac k et compression is disab led when the destination address matches the last source address register . ep 0 last source address com- pare mask ed (disab led) 1 last source address compare enab led note: zeros should be wr itten to all register bits e xcept the ep bit. pref erred address compare enab le address: 1110 1111 setting the ep bit in this register enab les a compar ison of the destination address of an incoming pac k et to the pref erred address register f or the e xpansion por t. p ac k et compression is disab led when the destination address matches the pref erred address register . ep 0 pref erred source address compare disab led 1 pref erred source address compare enab led note: zeros should be wr itten to all register bits e xcept the ep bit. t r ansceiv er interf ace changed interr upt enab le address: 1111 0000 when a bit is set, an interr upt is gener ated if the de vice connected to the corresponding por t changes from a quiet de vice to a non-quiet de vice or from a non- quiet de vice to a quiet de vice . t r ansceiv er 0 p a ui [3:0] t r ansceiv er 1 p a ui [7:4] t r ansceiv er 2 p a ui [11:8] t r ansceiv er 3 a ui and ra ui por ts qn 0 de vice connection changed t est mask ed (disab led) 1 de vice connection changed t est enab led j ab ber interr upt enab le address: 1111 0001 when a bit in this register is set, an indication of jab ber from a por t will cause an interr upt. tpn/spn 0 j ab ber interr upt mask ed (disab led) 1 j ab ber interr upt enab led 0 0 0 0 0 0 0 0 0 ep 0 0 0 0 0 0 d port read/write byte 0 byte 1 msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 ep ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 msb lsb 0 0 0 0 0 0 0 0 0 ep 0 0 0 0 0 0 d port read/write byte 0 byte 1 msb lsb 0 0 0 0 0 0 0 0 0 ep 0 0 0 0 0 0 d port read/write byte 0 byte 1 msb lsb x x x x q3 q2 q1 q0 d p or t read/wr ite msb lsb tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp 10 tp9 tp8 byte 0 byte 1 d port read/write msb lsb
AM79C983A 37 preliminary register bank 3: p or t contr ol register s these registers are accessed b y wr iting the bit patter n 0000 0011 into the c register . all registers can be read from as w ell as wr itten to . alter nativ e reconnection algor ithm enab le address: 1110 0000 the a ui p ar titioning/reconnection state machine can be prog r ammed f or the alter nativ e reconnection algo- r ithm (tr ansmit only). on reset, this register def aults to the standard reconnection algor ithm. pn/a ui/ra ui 0 standard reconnection algor ithm 1 alter nativ e reconnection algor ithm link t est enab le address 1110 0010 setting a bit in this register enab les the link t est func- tion f or the corresponding por t. this is only in eff ect when the imr2 de vice is interf aced to a quiet de vice . on reset, this register def aults to link t est enab led. tpn/spn 0 link t est function disab led 1 link t est function enab led link pulse t r ansmit enab le address: 1110 0011 setting a bit in this register enab les the corresponding por t to tr ansmit a link t est pulse . this is only in eff ect when the imr2 de vice is interf aced to a quiet de vice . on reset, this register def aults to link t est pulse t r ansmit enab led. tpn/spn 0 link t est pulse t r ansmit disab led 1 link t est pulse t r ansmit enab led a utomatic receiv er p olar ity re v ersal enab le address 1110 0100 setting a bit in this register enab les the quiet de vice to automatically in v er t the receiv e signal f ollo wing detec- tion of the t rst pac k et with in v er ted polar ity . this is done once after reset or link f ail. on reset, this register de- f aults to a utomatic receiv er p olar ity re v ersal disab led. tpn/spn 0 a utomatic receiv er p olar ity re v ersal disab led 1 a utomatic receiv er p olar ity re v ersal enab led sqe mask enab le address: 1110 0101 setting a bit in this register allo ws the corresponding por t to ignore activity on ci dur ing the sqe test windo w f ollo wing a tr ansmission on that por t. the sqe test win- do w is det ned b y ansi/ieee 802.3, section 7.2.2.2.4 as 6-bit times to 31-bit times f ollo wing the end of the pac k et. note that the sqe mask does not aff ect repor t- ing sqe tests on the sqe status register and the sqe t est change interr upt register . on reset, this reg- ister def aults to sqe t est mask disab led. pn/a ui/ra ui 0 sqe t est mask disab led 1 sqe t est mask enab led p or t enab le/disab le address 1110 0110 setting a bit in this register enab les the corresponding por t. on reset, the por ts def ault to enab led. pn/a ui/ra ui 0 disab le the corresponding por t 1 enab le the corresponding por t setting the ep bit will not disab le the e xpansion b us . ho w e v er , if the ep bit is not set, data carr ied on the e x- pansion b us that is addressed to a ma c will not be counted in the mib attr ib utes . p or t switching control address: 1110 0111 setting a bit in this register isolates the corresponding por t. all input signals to the corresponding por t and all inf or mation concer ning por t activity from the tr ansceiv er p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 msb lsb tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp 10 tp9 tp8 byte 0 byte 1 d port read/write msb lsb tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp 10 tp9 tp8 byte 0 byte 1 d port read/write tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp 10 tp9 tp8 byte 0 byte 1 d port read/write msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 ep ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 msb lsb
38 AM79C983A preliminary are ignored. this f eature is useful when implementing por t s witching. the imr2 de vice connected to the quiet de vice ser ial interf ace will still repor t correct status on the link and p olar ity leds . the por ts def ault to the xena v alue on reset. pn/a ui/ra ui 0 isolate the corresponding por t 1 connect the corresponding por t note: if a por t is isolated dur ing an incoming or tr ansmit- ted pac k et, repeating the pac k et is immediately stopped. if a por t is connected dur ing an incoming pac k et, the ac- tual connection is dela y ed until after the end of the pac k et. if a por t is connected while the imr2 de vice is repeating a pac k et, the connection is made immediately . extended distance enab le address: 1110 1000 setting a bit on this register lo w ers the input threshold on rxd of the corresponding quiet tr ansceiv er . this allo ws the use of a twisted pair cab le longer than 100 meters . this register is only in eff ect if the correspond- ing por t is connected to a quiet de vice . on reset, this register def aults to extended distance option disab led. tpn/spn 0 extended distance option disab led 1 extended distance option enab led a utomatic last source address intr usion control address: 1110 1001 a utomatic intr usion control disab les a por t automati- cally when a v alid pac k et (no errors) is receiv ed with a source address which is not a v alid address f or that por t. bef ore a bit on this register is set, the correspond- ing last source address register should contain a v alid address f or that por t. on reset, this register de- f aults to a utomatic intr usion control with last source address disab led. see note under a utomatic pref erred source address intr usion control . pn/a ui/ra u 0 a utomatic intr usion control with last source address disab led 1 a utomatic intr usion control with last source address enab led a utomatic pref erred source address intr usion control address: 1110 1010 a utomatic intr usion control disab les a por t automatically when a v alid pac k et (no errors) is receiv ed with a source address which is not a v alid address f or that por t. bef ore a bit on this register is set, the corresponding pref erred address register should contain a v alid address f or that por t. on reset, this register def aults to a utomatic intr usion control with pref erred source address disab led. pn/a ui/ra ui 0 a utomatic intr usion control with pref erred source address disab led 1 a utomatic intr usion control with pref erred source address enab led note: the a utomatic pref erred source address intr u- sion control register and the a utomatic last source ad- dress intr usion control register w or k together . if intr usion on a por t is not enab led on either register , intr usion control is not perf or med f or that por t. if intr usion on a por t is en- ab led on only one of the intr usion control registers , intr u- sion control is based on the corresponding enab led register . if intr usion on a por t is enab led on both intr usion control registers , the por t is disab led if the source address f ails to match both the last source address register and the pref erred source address register . last source address loc k control address: 1110 1011 whene v er the source address of an incoming pac k et is diff erent from the last source address register , the ne w source address is wr itten into the last source ad- dress register . setting a bit on this register disab les automatic updating of the last source address regis- ter based on the last receiv ed pac k et. the last source address register can still be wr itten into via the node processor interf ace . on reset, this register def aults to last source address loc k disab led. note that a re- peater that uses last source address loc k control will not comply with ietf rfc 1516. p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 msb lsb tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp 10 tp9 tp8 byte 0 byte 1 d port read/write msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read/ write byte 0 byte 1 msb lsb p7 p6 p5 p4 p3 p2 p1 p0 0 ep ra ui a ui p11 p10 p9 p8 d port read/write byte 0 byte 1 msb lsb
AM79C983A 39 preliminary pn/a ui/ra ui /ep 0 last source address loc k disab led 1 last source address loc k enab led note: setting a bit on this register in v alidates the cor- responding source address changes register . register bank 4: p or t status register s these registers are accessed b y wr iting 0000 0100 to the c register . p ar titioning status of p or ts address: 1110 0000 these bits indicate the par tition status of the corre- sponding por ts . p or ts that are par titioned will tr ansmit pac k ets . ho w e v er , the imr2 de vice will not repeat pac k ets receiv ed b y a par titioned por t. pn/a ui/ra ui 0 p or t par titioned 1 p or t connected link t est status of p or ts address: 1110 0010 the register bits indicate the link t est status of the cor- responding por ts . the bit setting is based on data re- ceiv ed b y the quiet de vice . theref ore , the bit setting is in v alid if a non-quiet tr ansceiv er is used f or the por t. tpn/spn 0 link t est f ailed 1 link t est passed loopbac k error status address: 1110 0011 when a pac k et is tr ansmitted, the do signal is looped bac k to the imr2 de vice through the corresponding di pins . when a bit on this register is set, data is not being looped bac k to the imr2 de vice . pn/a ui/ra ui 0 no loopbac k error 1 loopbac k error note: the ra ui bit is not v alid when the ra ui por t is in the re v erse mode . receiv e p olar ity status address: 1110 0100 each register bit represents the receiv e polar ity status of the corresponding por t. the bit setting is based on data receiv ed from the quiet de vice through the ser ial interf ace . if another tr ansceiv er de vice is used, the bit setting re? ects what is on the corresponding sd a t a. tpn/spn 0 p olar ity correct 1 p olar ity re v ersed sqe t est status address: 1110 0101 these register bits re? ect the status of the last pac k et receiv ed from the corresponding por t. the ra ui bit is not v alid when the ra ui por t is in the re v erse mode . pn/a ui/ra ui 0 no sqe t est error 1 sqe t est error register bank 5: rmon register s the rmon registers can be accessed b y wr iting to ad- dress 0000 0101 and then accessing the individual reg- isters . the rmon registers are 32-bit counters and comply with etherstatsentr y of the statistics g roup of the rmon mib (rfc 1757) or etherhistor yentr y of the histor y g roup of rfc 1757. the y are 4 b ytes long and are read lo w order b yte to high order b yte . the rmon registers can usually only be read. ho w- e v er , the y can be wr itten to when the repeater reset bit or the management reset bit on the de vice cont g- ur ation register is set. etherstatsoctets address: 1110 0000 the v alue in this register represents the total n umber of octets receiv ed (e xcluding preamb le bits , b ut including fcs bits) b y the imr2 de vice . etherstatspkts address: 1110 0001 the v alue in this register represents the total n umber of pac k ets receiv ed b y the imr2 de vice . p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read byte 0 byte 1 lsb msb tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp9 tp8 byte 0 byte 1 d port read lsb msb tp10 p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read byte 0 byte 1 msb lsb tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 sp3 sp2 sp1 sp0 tp11 tp 10 tp9 tp8 byte 0 byte 1 d port read lsb msb p7 p6 p5 p4 p3 p2 p1 p0 0 0 ra ui a ui p11 p10 p9 p8 d port read byte 0 byte 1 msb lsb
40 AM79C983A preliminary etherstatsbroadcastpkts address: 1110 0010 the v alue in this register represents the total n umber of v alid pac k ets receiv ed that w ere addressed to a broadcast address . etherstatsmulticastpkts address: 1110 0011 the v alue in this register represents the total n umber of v alid pac k ets receiv ed that w ere addressed to a m ulticast address . etherstatscrcalignerrors address: 1110 0100 the v alue in this register represents the total n umber of pac k ets receiv ed that w ere betw een 64 and 1518 octets , inclusiv e , and had either fcs errors or alignment errors . etherstatsundersiz epkts address: 1110 0101 the v alue in this register represents the total n umber of pac k ets receiv ed that w ere less than 64 octets long, b ut w ere otherwise error free . etherstatsov ersiz epkts address: 1110 0110 the v alue in this register represents the total n umber of pac k ets receiv ed that w ere g reater than 1518 octets long, b ut w ere otherwise error free . etherstatsf r agments address: 1110 0111 the v alue in this register represents the total n umber of pac k ets receiv ed that w ere less than 64 octets long, not including the preamb le or sfd , and had either an fcs error or an alignment error . etherstatsj ab bers address: 1110 1000 the v alue in this register represents the total n umber of pac k ets that w ere g reater than 1518 octets long and had either fcs errors or alignment errors . note: this diff ers from the ieee det nition of j ab ber . etherstatscollisions address: 1110 1001 the v alue in this register represents the total n umber of collisions on the imr2 de vice . etherstats64octets address: 1110 1010 the v alue in this register represents the total n umber of pac k ets (including error pac k ets) that w ere 64 octets long. etherstats65to127octets address: 1110 1011 the v alue in this register represents the total n umber of pac k ets (including error pac k ets) that w ere 65 octets to 127 octets long inclusiv e . etherstats128to255octets address: 1110 1100 the v alue in this register represents the total n umber of pac k ets (including error pac k ets) that w ere 128 octets to 255 octets long inclusiv e . etherstats256to511octets address: 1110 1101 the v alue in this register represents the total n umber of pac k ets (including error pac k ets) that w ere 256 octets to 511 octets long inclusiv e . etherstats512to1023octets address: 1110 1110 the v alue in this register represents the total n umber of pac k ets (including error pac k ets) that w ere 512 octets to 1023 octets long inclusiv e . etherstats1024to1518octets address: 1110 1111 the v alue in this register represents the total n umber of pac k ets (including error pac k ets) that w ere 1024 octets to 1518 octets long inclusiv e . activity address: 1111 0000 the v alue in this register represents the total n umber of octets that w ere activ e on the imr2 de vice . register bank 7: mana g ement suppor t these registers control pac k et compression and error sampling. the management suppor t registers can be accessed b y wr iting 0000 0111 to the c register and then wr iting the register address to the c register . de vice id address: 1110 0000 the de vice id register is a read/wr ite register . it is an 8-bit register and contains the assigned id n umber of the imr2 de vice . this n umber is tr ansmitted as par t of the tag t eld b y the p ac k et repor t p or t. sample error status address: 1110 0010 sample error status giv es statistical data on pac k ets that ha v e errors . it is a 4-deep 8-b yte fifo . each read re- quires accessing the data register eight times . the ac- cess can jump to the ne xt le v el of the fifo in the middle of a read b y wr iting an y v alue to the node processor por t with the c/ d pin high. if the node processor por t is ac- cessed (with the c/ d pin lo w) after the last b yte is read,
AM79C983A 41 preliminary the register jumps to the ne xt le v el automatically . the data f or mat is as f ollo ws: e p ac k et 0 - empty 1 - v alid n3-0 p or t number vl v er y long ev ent dre data rate error rnt runt p ac k et s shor t ev ent l long ev ent a alignment error fcs fcs error bytes 2-7 source address . it is read lo w order b yte to high order b yte . note: the fifo is emptied b y reading. if the fifo is full, nothing more is recorded in sample error status . if the fifo is empty (bit e = 0), there is nothing in the re- maining 7 b ytes; theref ore , the ne xt access will be the t rst b yte of the 8-b yte register . repor t p ac k et siz e address: 1110 0011 repor t p ac k et siz e is a tw o-b yte register . the ele v en least signit cant bits are used. it sets the length of the or iginal pac k et (in octets) that is tr ansmitted o v er the p ac k et repor t p or t. the ls byte is accessed t rst. the limits are 14 b ytes (binar y 000000001110) and 1535 b ytes (binar y 10111111111). if the register is set at less than 14, 14 b ytes of the or iginal pac k et are tr ans- mitted o v er the p ac k et repor ts p or t. if the register is set at g reater than 1535 b ytes , all of the or iginal pac k et is sent o v er the p ac k et repor t p or t. st a ts control address: 1110 0100 st a ts control is a 1-b yte register . it sets the oper ation of the p ac k et repor t p or t and the ra ui por t. t 0 p ac k et tagging is disab led 1 p ac k et tagging is enab led f 0 appending of a ne w fcs dur ing por t tag- ging is disab led 1 appending of a ne w fcs dur ing por t tag- ging is enab led register banks 16 thr ough 30: p or t attrib ute register s p or t attr ib ute registers are accessed b y wr iting the ap- propr iate por t n umber into the c register , f ollo w ed b y the attr ib ute n umber . the tab le belo w sho ws the corre- sponding register bank f or each por t. except f or the last source address register and the pref erred source register , all registers are f our b ytes long and read only unless special conditions are met. the last source address register and the pref erred source address register are six b ytes long and their contents can be wr itten and read. once the c register is prog r ammed with a v alid por t and attr ib ute n umber , the corresponding attr ib ute is tr ansf erred to a holding register upon reading the t rst b yte . subsequent accesses to the d register access the v alue in a least signit cant to most signit cant b yte order . dur ing a read, once the last b yte is read, the at- tr ib ute v alue is re-tr ansf erred to the holding register and the sequence can be restar ted. when wr iting the last source address register and the pref erred source register , if the sequence is abor ted pr ior to the 6th consecutiv e wr ite cycle , the register v alue is not altered. the sequence (read or wr ite) ma y be abor ted and restar ted b y prog r amming the c register . e 0 0 0 n3 n2 n1 n0 0 vl dre rnt s l a fcs bit 23 bit 16 bit 56 d port read/write byte 0 byte 1 msb lsb byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 bit 63 bit 0 bit 15 bit 8 d p or t read/wr ite lsb byte 0 byte 1 bit 7 msb 0 t f 0 0 0 0 0 d p or t read / wr ite msb lsb register bank access p or t 0001 0000 0 0001 0001 1 0001 0010 2 0001 0011 3 0001 0100 4 0001 0101 5 0001 0110 6 0001 0111 7 0001 1000 8 0001 1001 9 0001 1010 10 0001 1011 11 0001 1100 a ui 0001 1101 ra ui 0001 1110 expansion bus (activity recorded when ma cen is tr ue)
42 AM79C983A preliminary the contents of all attr ib ute registers are maintained dur ing hardw are or softw are reset. these attr ib utes and their det nitions comply with the ieee 802.3 repeater management standard, section19 ( la y er management f or 10 mb/s baseband repeaters) . a br ief descr iption of attr ib utes is included here f or ref erence only . f or more details ref er to the ieee document. an imr2-based hub can be designed that will comply with ietf rfc 1515 and rfc 1516. the p or t attr ib ute registers can be wr itten into if one of tw o conditions are met. the t rst is when either the m bit or the r bit on the de vice cont gur ation register is set. the second is when the corresponding por t is disab led. readab le f r ames address: 1110 0000 readab le f r ames is a read-only attr ib ute that counts the n umber of v alid fr ames detected b y the por t. v alid fr ames are from 64 b ytes to 1518 b ytes in length, ha v e a v alid fr ame crc , and are receiv ed without a collision. this attr ib ute is a 32-bit counter with a minim um roll- o v er time of 80 hours . readab le octets address: 1110 0001 readab le octets is a read-only attr ib ute that counts the n umber of octets receiv ed on each por t. this n umber is deter mined b y adding the fr ame length to this register at the completion of e v er y v alid fr ame . this attr ib ute is a 32- bit counter with a minim um rollo v er time of 58 min utes . f r ame chec k sequence (fcs) errors address: 1110 0010 f r amechec ksequence (fcs) errors is a read-only attr ib ute that counts the n umber of fr ames detected on each por t with an in v alid fr ame chec k sequence . this counter is incremented on each fr ame of v alid length (64 b ytes to 1518 b ytes) that does not suff er a collision dur ing the fr ame . this counter is incremented on each in v alid fr ame . ho w e v er , it is not incremented f or fr ames with both fr aming errors and fr ame chec k sequence errors . this attr ib ute is a 32-bit counter with a minim um rollo v er time of 80 hours . alignment errors address: 1110 0011 alignment errors is a read-only attr ib ute that counts the n umber of fr ames detected on each por t with an fcs error and a fr aming error . this counter is incremented on each fr ame of v alid length (64 b ytes to 1518 b ytes) that does not suff er a collision dur ing the fr ame . f r ames that ha v e both fr aming errors and fcs errors are counted b y this attr ib ute , b ut not b y the f r ame chec k sequence errors attr ib ute . this attr ib ute is a 32-bit counter with a minim um rollo v er time of 80 hours . f r ames t oo long address: 1110 0100 f r ames t oo long is a read-only attr ib ute that counts the n umber of fr ames that e xceed the maxim um v alid pac k et length of 1518 b ytes . this attr ib ute is a 32-bit counter with a minim um rollo v er time of 61 da ys . bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb
AM79C983A 43 preliminary shor t ev ents address: 1110 0101 shor t ev ents is a read-only attr ib ute that counts the n umber of instances where activity is detected with a dur ation less than the shor tev entmaxtime (74-82 bit times). this attr ib ute is a 32-bit counter with a minim um rollo v er time of 16 hours . runts address: 1110 0110 runts is a read-only attr ib ute that counts the n umber of instances where activity is detected with a dur ation g reater than the shor tev entmaxtime (74-82 bit times , b ut less than the minim um v alid fr ame time (512-bit times , or 64 b ytes). this attr ib ute is a 32-bit counter with a minim um rollo v er time of 16 hours . note: runts usually indicate collision fr agments , a nor mal netw or k e v ent. in cer tain situations associated with large diameter netw or ks , a percentage of r unts ma y e xceed v alidp ac k etmintime . collisions address: 1110 0111 collisions is a read-only attr ib ute that counts the n um- ber of instances where a carr ier is detected on the por t, and a collision is detected. this attr ib ute is a 32-bit counter with a minim um rollo v er time of 16 hours . late ev ents address: 1110 1000 late ev ents is a read-only attr ib ute that counts the n umber of instances where a collision is detected after the lateev entthreshold (480-565 bit times) in the fr ame . this e v ent will be counted both b y the late ev ents attr ib ute , as w ell as the collisions attr ib ute . this attr ib ute is a a 32-bit counter with a minim um rollo v er time of 81 hours . v er y long ev ents address: 1110 1001 v er y long ev ents is a read-only attr ib ute that counts the n umber of times the tr ansmitter is activ e in e x- cess of the ma u j ab ber loc kup protection (mjlp) timer (4 ms - 7.5 ms). this attr ib ute is a 32-bit counter with a minim um rollo v er time of 198 da ys . data rate mismatches address: 1110 1010 data rate mismatches is a read-only attr ib ute that counts the n umber of occurrences where the frequency or data r ate of the incoming signal is detectab ly diff er- ent from the local tr ansmit frequency . t o be counted, the incoming pac k et m ust be at least 512 b ytes and not in collision. the attr ib ute is a 32-bit counter with a min- im um rollo v er time of 80 hours . note: the r ate at which the data rate mismatches attr ib ute will increment will depend on the magnitude of the diff erence betw een the receiv ed signal cloc k and the local tr ansmit frequency . bit 7 bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 msb bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb
44 AM79C983A preliminary a uto p ar titions address: 1110 1011 a uto p ar titions is a read-only attr ib ute that counts the n umber of instances where the repeater has par titioned this por t from the netw or k. this attr ib ute is a 32-bit counter that is incremented on each such e v ent. the appro ximate minim um time betw een counter rollo v ers is 20 da ys . source address changes address: 1110 1100 source address changes is a read-only attr ib ute that counts the n umber of times the source address t eld of v alid fr ames receiv ed on a por t changes . this attr ib ute is a 32-bit counter with a minim um rollo v er of 81 hours . note: this ma y indicate whether a link is connected to a single dte or another m ulti-user segment. readab le broadcast f r ames address: 1110 1101 the counter is incremented b y one each time this por t receiv es an error-free broadcast fr ame . last source address address: 1110 1110 last source address is a read/wr ite attr ib ute and is the source address of the last readab le fr ame receiv ed b y this por t. this 6-b yte register ma y be read from or wr itten to . this f eature allo ws the softw are to preset this attr ib ute to the kno wn node id f or a single node segment. a change in the contents of this register w ould then signal an anom- aly . this will cause the source address changes at- tr ib ute to increment. fur ther more , setting the respectiv e p a ui/a ui/ra ui p or t source address change interr upt enab le bit (in the p or t control regis- ters) can be used to gener ate a hardw are interr upt to signal the softw are to automatically disab le this por t. readab le multicast f r ames address: 1110 1111 the counter is incremented b y one each time this por t receiv es an error-free m ulticast fr ame . broadcast fr ames are not counted. pref erred source address address: 1111 0000 the address prog r ammed into this register is compared with the incoming source address to gener ate a source address changed interr upt. this is a 6-b yte w ord. the oper ation will abor t if all 6 b ytes are not wr itten. bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb bit 7 bit 0 bit 47 bit 40 d p or t read/wr ite msb lsb byte 0 byte 1 byte 4 byte 5 byte 2 byte 3 bit 0 bit 31 bit 24 d p or t read lsb byte 0 byte 1 byte 2 byte 3 bit 7 msb bit 7 bit 0 bit 47 bit 40 d p or t read/wr ite msb lsb byte 0 byte 1 byte 4 byte 5 byte 2 byte 3
AM79C983A 45 preliminary system applications imr2 to quiet connection the imr2 device provides a system solution to design- ing repeaters. it can be used with the quiet transceivers to design 10base-t hubs or with other types of maus for 10base2 or 10base-fl hubs. the mau types can be mixed to design a hub that supports multiple media types. the imr2 device connects di- rectly to the quiet device transceivers. 7 shows the simplited connection. three quiet devices may be connected to a single imr2 device for 12 ports. only one connection is shown for simplicity. other media the imr2 device, with some supporting circuitry, can be connected to the aui port of any mau device. thus, it can support 10base2 and 10base-fl. the example in 8 shows a paui port connected to a 10base-fl trans- ceiver (ml4663). for the ml4663, signals tx, rx, and col are equivalent to the aui signals do, di, and ci. the 360 -w resistors are required by the ml4663 drivers. mac interface the imr2 device can be connected to a mac using either the raui port or the pr port. the raui port supports a direct connection. the pr port requires some glue logic. raui port when the raui port is to be connected to a mac, it should be contgured in reverse mode and connected as shown in 9 (a). notice that rdi is connected to do of the mac and rdo is connected to di. this is be- cause the reverse contguration only affects rci. 9 (b) shows the normal aui contguration for reference. pr port contguration the pr port may be connected to the gpsi port of a mac. communication with the mac involves both the pr port and the expansion bus. the pr port connects to the receive side of the mac and the expansion bus connects to the transmit side. an example of the mac connection is shown in 10. here the imr2 device is connected to the sia interface of the am79c90 (c-lance). ma cen , dat, and eclk are bus signals. therefore, the and gates and buffers to these signals must be open-collector or open-drain. the or gate for rena satistes the loopback require- ments for the c-lance.
46 AM79C983A preliminary figure 7. simplit ed 10b ase-t connection quiet typical imr2 tp connector tp connector tp connector tp connector 100 w 110 w 100 w 110 w 100 w 100 w 13k w 110 w 110 w txd0+ txd0- rxd0+ rxd0- txd1- rxd1+ rxd1- txd2+ txd2- rxd2+ rxd2- txd3+ txd3- rxd3+ rxd3- txd1+ rext rst clk pdo0 pdi0 pci0 pdo0 pdi0 pci0 pdo1 pdi1 pci1 pdo1 pdi1 pci1 pdo2 pdi2 pci2 pdo2 pdi2 pci2 pdo3 pdi3 pci3 pdo3 pdi3 pci3 av dd mclk rst 19879b -11 note : common mode chok es ma y be required.
AM79C983A 47 preliminary figure 8. p a ui interface to non-quiet de vice t ransceiver figure 9. ra ui p or t inter connections pdo pdi pci am79c983 16 k w 10k 0.1 f 0.1 f 330 w 100 w 100 w ml4663 tx+ tx rx+ rx col+ col 360 w 360 w 10k 78 w 10k 0.1 f 360 w 360 w 10k 78 w 19879b -12 am79c983 a m7996 am79c940 do+ do di+ di ci+ ci 40 w 40 w 40 w 40 w 40 w 40 w 0.1 m f 0.1 m f 0.1 m f rdi+ rdi rdo+ rdo rci+ rci di+ di do+ do ci+ ci 40 w 40 w 0.1 m f 0.1 m f 40 w 40 w 40 w 40 w 0.1 m f 39 w ?150 w +9 v a) reverse mode (with mac) b) normal mode (with mau) am79c983 rdi+ rdi rdo+ rdo rci+ rci 19879b -13
48 AM79C983A preliminary figure 10. pr p or t connection to an am79c90 c-lance p or t switc hing p or t s witching allo ws the mo v ement of individual por ts betw een m ultiple ether net collision domains via soft- w are . this capability enab les the netw or k manager to optimiz e netw or k perf or mance b y dynamically balanc- ing the loads on a netw or k. as an e xample , a por t e x- hibiting a high le v el of activity can be mo v ed to a less congested collision domain. the method of implementing por t s witching with the imr2/quiet chip set is to connect a single tr ansceiv er por t to m ultiple imr2 de vices . the n umber of imr2 de- vices will equal the n umber of bac kplanes suppor ted in the hub . 11 is a simplit ed schematic sho wing a hub with three separ ate bac kplanes . only one quiet de- vice is sho wn f or simplicity , although it is e xpected that most applications will use three quiet de vices to en- ab le 12 por t m ultiples . the f ollo wing discussion of por t s witching will con- sider only por t 0; although, it is equally applicab le to all of the por ts . at an y time , p a ui [ 0 ] is enab led on one , and only one , imr2 de vice . as a result, por t 0 is tr ans- f erred to whiche v er imr2 de vice has p a ui [ 0 ] enab led. the other tw o imr2 de vices will ha v e p a ui [ 0 ] disab led with pdo [ 0 ] in a high impedance state . t o mo v e por t 0 to another bac kplane , the softw are will disab le p a ui [ 0 ] on the activ e imr2 de vice and enab le p a ui [ 0 ] on the targeted imr2 de vice that represents the desired bac kplane . pseudo a ui por ts can be disab led or enab led b y setting the appropr iate bit in the p or t switching control register . although there are m ultiple imr2 de vices , only one has management control of the quiet de vices . 11 sho ws imr2 de vice 0 ha ving management control. the other tw o de vices do not ha v e an y control o v er the cont gur a- tion of the quiet de vices . the n umber of imr2 de vices that can be connected to- gether is limited b y the load on the p a ui dr iv ers . the p a ui will oper ate reliab ly with a load up to 100 pf . on a system that uses soc k ets f or the imr2 de vices , the maxim um n umber of de vices is six. this n umber can in- crease as long as the total load capacitance is k ept belo w 100 pf . col jam macen dat 4.9 k w +5 v eclk clock generator clsn rclk rx rena tena tx tcl am79c90 (c-lance) pclk pdrv pdat penai penao 19879b -14
AM79C983A 49 preliminary figure 11. p or t switc hing cont guration a m 7 9 c 9 8 8 backplane 0 am79c983 imr2 0 backplane 1 am79c983 imr2 1 am79c983 imr2 2 backplane 2 pdo pdi pci pdo pdi pci pdo pdi pci pdo pdi pci sdata[0] dir[1] pdo pdi pci pdo pdi pci pdo pdi pci pdo pdi pci sdata dir tx rx tx rx tx rx tx rx port 0 port 1 port 2 port 3 pdo pdi pci pdo pdi pci pdo pdi pci pdo pdi pci pdo pdi pci pdo pdi pci pdo pdi pci pdo pdi pci 19879b -15
50 AM79C983A preliminary absolute maximum ra tings stor age t emper ature . . . . . . . . . . . .. e65 c to +150 c ambient t emper ature under bias . . . . . . . . . 0 to 70 c supply v oltage ref erenced to a v ss or d v ss (a v dd , d v dd ) . . . . . . . . . . . . .e0.3 to +6v stresses abo v e those listed under absolute maxi- mum ra tings ma y cause per manent de vice f ailure . functionality at or abo v e these limits is not implied. expo- sure to absolute maxim um ratings f or e xtended per iods ma y aff ect reliability . prog r amming conditions ma y diff er . opera ting ranges commercial (c) de vices t emper ature (t a) . . . . . . . . . . . . . .0 c to + 70 c supply v oltages (v dd ) . . . . . . . . . . . . . +5 v 5% oper ating r anges det ne those limits betw een which the functionality of the de vice is guar anteed. dc chara cteristics o ver operating rang es unless otherwise specit ed p arameter symbol p arameter description t est conditions min max unit digital i/o v il input low voltage - -0.5 0.8 v v ih input high voltage - 2.0 0.5+v dd v v ol output low voltage i ol =4.0 ma - 0.4 v v oh output high voltage i oh =-0.4 ma 2.4 - v i il input leakage current 0 AM79C983A 51 preliminary switching chara cteristics o ver operating rang es unless otherwise specit ed p arameter symbol p arameter description t est conditions min max unit clock and reset timing t mclk mclk cloc k p er iod 49.995 50.005 ns t mclkh mclk cloc k high 20 30 ns t mclkl mclk cloc k lo w 20 30 ns t mclkr mclk rise time - 10 ns t mclkf mclk f all time - 10 ns t eclkh eclk high (note 2) 0.4 t eclk 0.6 t eclk ns t eclkl eclk lo w (note 2) 0.4 t eclk 0.6 t eclk ns t ecrr eclk rise time (when receiving d a t) (note 1) - 10 ns t ecrf eclk f all time (when receiving d a t) (note 1) - 10 ns t ectr eclk rise time (when t r ansmitting d a t) (note 1) - 10 ns t ectf eclk f all time (when t r ansmitting d a t) (note 1) - 10 ns t rst reset pulse width 4 - m s t rstp reset pulse width on p o w er-up 150 - m s t rstset reset input setup time with respect to mclk 20 - ns t rsthld reset input hold time with respect to mclk 0 - ns (r)aui port timing t do td mclk high to do t oggle - 30 ns t do tr do rise time (note 1) - 7.0 ns tdo tf do f all time (note 1) - 7.0 ns t dorm do+, do- rise and f all time mismatch - 1.0 ns t doetd do end of t r ansmission 275 375 ns t pw od i di pulse width accept/reject |v in |>|v asq | (note 3) 15 45 ns t pwkdi di pulse width not to t ur n off inter nal carr ier sense |v in |>|v asq | (note 4) 136 220 ns t pw oc i ci pulse width accept/reject threshold |v in |>|v asq | (note 5) 8 26 ns t pwkci ci pulse width not to t ur n off threshold |v in |>|v asq | (note 6) 80 160 ns t citr rci rise time (in re v erse mode) (note 1) - 7.0 ns t citf rci f all time (in re v erse mode) (note 1) - 7.0 ns t cirm rci+, rci- rise and f all time mismatch (ra ui in re v erse mode) - 1.0 ns paui port timing t pdo td mclk high to do t oggle - 30 ns t pdoetd pdo end of t r ansmission (note 1) 275 375 ns t pw opd i pdi pulse width accept/reject (note 7) |v in |>|v asq | 15 45 ns t pwkpdi di pulse width not to t ur n off inter nal carr ier sense (note 8) |v in |>|v asq | 136 220 ns t pw opci ci pulse width accept/reject threshold (note 9) |v in |>|v asq | 8 26 ns t pwkpci ci pulse width not to t ur n off threshold (note 10) |v in |>|v asq | 80 160 ns expansion bus timing t mhrl mclk high to req dr iv en lo w c l =100pf 10 40 ns t mhrh mclk high t o req dr iv en high c l =100pf 10 40 ns
52 AM79C983A preliminary notes: 1. p ar ameter is not tested. 2. eclk is dependent on the frequency of the data on the activ e por t. 3. (r)di pulses narro w er than tpw odi (min) will be rejected; (r)di pulses wider than tpw odi (max) will tur n inter nal (r)di car- r ier sense on. 4. (r)di pulses narro w er than tpwkdi (min) will maintain inter nal (r)di carr ier sense on; (r)di pulses wider than tpwkdi(max) will tur n inter nal (r)di carr ier sense off . 5. (r)ci pulses narro w er than tpw oci (min) will be rejected; (r)ci pulses wider than tpw oci (max) will tur n inter nal (r)ci car- r ier sense on. 6. (r)ci pulses narro w er than tpwkci (min) will maintain inter nal (r)ci carr ier sense; (r)ci pulses longer than tpwkci (max) will tur n inter nal (r)ci carr ier sense off . 7. pdi pulses narro w er than tpw opdi (min) will be rejected; pdi pulses wider than tpw opdi (max) will tur n inter nal pdi carr ier sense on. t mhdr mclk high to d a t/j am dr iv en c l =100pf 10 40 ns t mhdz mclk high t o d a t/j am not dr iv en c l =100pf 14 40 ns t mdset d a t/j am setup time to mclk 10 - ns t mdhold d a t/j am hold time from mclk 10 - ns t maset col / a ck setup time to mclk 5 - ns t mahld col / a ck hold time to mclk 14 - ns t eldr eclk lo w to d a t switching c l =100pf - 20 ns t edset d a t setup to eclk 10 - ns t edhold d a t hold time from eclk 14 - ns microprocessor interface timing t cds c/ d setup time with respect to rd / wr leading edge 10 - ns t cdh c /d hold time with respect to rd / wr rising edge 0 - ns t css cs setup time with respect to rd / wr f all- ing edge 10 - ns t csh cs hold time with respect to rd / wr rising 0 - ns t rd yd rd y leading edge dela y c l =100pf - 25 ns t rd yh rd y high to rd / wr rising 0 - ns t dout data out to rd y high c l =100pf 50 - ns t doh data out hold after rd high c l =100pf 10 50 ns t dis data in setup time with respect to wr ris- ing edge 25 - ns t rest rest p er iod betw een mpi oper ations (time betw een the ear liest cs / rd / wr going high to the ne xt cs / rd / wr going lo w , whiche v- er is the latest 150 - ns t dih data in hold after wr high 0 - ns management port timing t msso mclk to sd a t a 10 40 ns t msdo mclk to dir[1:0] 10 40 ns t msssu sd a t a setup time 10 - ns t msshd sd a t a hold time 10 - ns packet report port timing t pr v pclk lo w to pd a t switching - 20 ns p arameter symbol p arameter description t est conditions min max unit
AM79C983A 53 preliminary 8. pdi pulses narro w er than tpwkpdi (min) will maintain inter nal pdi carr ier sense on; pdi pulses wider than tpwkpdi (max) will tur n inter nal pdi carr ier sense off . 9. pci pulses narro w er than tpw opci (min) will be rejected; pci pulses wider than tpw opci (max) will tur n inter nal pci carr ier sense on. 10. pci pulses narro w er than tpwkpci (min) will maintain inter nal pci carr ier sense on; pci pulses wider than tpwkpci (max) will tur n inter nal pci carr ier sense off . 11. squelch thresholds change propor tionately with v dd .
54 AM79C983A preliminary key to switching waveforms switching waveforms figure 12. master clock (mclk) timing figure 13. expansion bus asynchronous clock (eclk) timing ks00010 must be steady may change from h to l may change from l to h does not apply don?t care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs t mclk t mclkh t mclkl 19879b-16 t eclk t eclkh t eclkl 19879b-17
AM79C983A 55 preliminary switching w a veforms figure 14. expansion bus input timing - sync hr onous mode figure 15. expansion bus output timing - sync hr onous mode t mdset t mdhold in *tclk illustrates internal imr2 chip clock phase relationships mclk tclk* req ack col dat/jam 19879b -18 out t mhrh t mhrl t maset t mahld t maset t mhdz t mhdr mclk tclk* req ack col dat/jam *tclk illustrates internal imr2 chip clock phrase relationships req ack col 19879b -19
56 AM79C983A preliminary switching w a veforms figure 16. expansion p or t collision timing - sync hr onous mode figure 17. p ac ket repor t p or t timing figure 18. expansion p or t input timing - async hr onous mode tclk* req ack dat/jam col mclk *tclk illustrates internal imr2 chip clock phrase relationships t mhrh t mahld t mhrl t maset t maset 19879b -20 pclk pdat penao t dprv 19879b -21 t edset t edhold in eclk req ack col dat 19879b -22
AM79C983A 57 preliminary switching w a veforms figure 19. expansion p or t output timing - async hr onous mode figure 20. p a ui pdo t ransmit figure 21. p a ui pci receive eclk req ack col dat t eldr 19879b -23 t pdotd mclk pdo 19879b -24 t pwkpci v asq t pwkpci pci t pwopci 19879b -25
58 AM79C983A preliminary switching w a veforms figure 22. p a ui receive figure 23. (r)a ui timing figure 24. (r)a ui receive t pwkpdi v asq t pwkpdi pdi t pwopdi 19879b -26 t dotd t dotr t dotf t doetd mclk do+ doe 19879b -27 t pwkdi v asq t pwkdi di or rdi t pwodi 19879b -28
AM79C983A 59 preliminary switching w a veforms figure 25. micr opr ocessor bus interface timing t cds t css t csh t cdh t rest t rdyd t rdyh t rest t doh t dih t dis read data write data t dout c/ d cs rd , wr rdy d7C0 d7C0 19879b -29
60 AM79C983A preliminary physical dimensions* pqb 132 132-pin plastic quad flat p ac k (measured in inches) revision summary this re vision (b) re? ects changes to figures 4, 7, and 8. changes ha v e also been made to the order ing inf or mation page , dc char acter istics and switching char acter istics tab les . also , the t ab le of contents has been mo v ed to page 7. no other technical changes ha v e been made . t rademarks cop yr ight ? 1997 adv anced micro de vices , inc. all r ights reser v ed. amd , the amd logo , and combinations thereof , and imr2, quiet , himib , p a ui, and ra ui are tr ademar ks of adv anced micro de vices , inc. product names used in this pub lication are f or identit cation pur poses only and ma y be tr ademar ks of their respectiv e companies . pin 132 pin 99 pin 66 pin 1 i.d. 16-038-pqb pqb132 db87 7-26-94 ae top view 1.097 1.103 0.947 0.953 1.075 1.085 1.097 1.103 0.008 0.012 pin 33 1.075 1.085 0.947 0.953 0.025 basic 0.160 0.180 0.80 ref bottom view 0.130 0.150 0.020 0.040 seating plane

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